1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_HAS_DEBUG_VIRTUAL
7 select ARCH_HAS_DEVMEM_IS_ALLOWED
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_SET_MEMORY
10 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
11 select ARCH_HAS_STRICT_MODULE_RWX if MMU
12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
13 select ARCH_HAVE_CUSTOM_GPIO_H
14 select ARCH_HAS_GCOV_PROFILE_ALL
15 select ARCH_MIGHT_HAVE_PC_PARPORT
16 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
17 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_USE_BUILTIN_BSWAP
20 select ARCH_USE_CMPXCHG_LOCKREF
21 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_EXTABLE_SORT if MMU
23 select CLONE_BACKWARDS
24 select CPU_PM if (SUSPEND || CPU_IDLE)
25 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
26 select DMA_NOOP_OPS if !MMU
28 select EDAC_ATOMIC_SCRUB
29 select GENERIC_ALLOCATOR
30 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
31 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
32 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select HANDLE_DOMAIN_IRQ
45 select HARDIRQS_SW_RESEND
46 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
47 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
48 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
49 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
50 select HAVE_ARCH_MMAP_RND_BITS if MMU
51 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
52 select HAVE_ARCH_TRACEHOOK
53 select HAVE_ARM_SMCCC if CPU_V7
54 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
55 select HAVE_CC_STACKPROTECTOR
56 select HAVE_CONTEXT_TRACKING
57 select HAVE_C_RECORDMCOUNT
58 select HAVE_DEBUG_KMEMLEAK
59 select HAVE_DMA_API_DEBUG
60 select HAVE_DMA_CONTIGUOUS if MMU
61 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
62 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
63 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
64 select HAVE_EXIT_THREAD
65 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
66 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL && !CC_IS_CLANG)
67 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
68 select HAVE_FUTEX_CMPXCHG if FUTEX
69 select HAVE_GCC_PLUGINS
70 select HAVE_GENERIC_DMA_COHERENT
71 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
72 select HAVE_IDE if PCI || ISA || PCMCIA
73 select HAVE_IRQ_TIME_ACCOUNTING
74 select HAVE_KERNEL_GZIP
75 select HAVE_KERNEL_LZ4
76 select HAVE_KERNEL_LZMA
77 select HAVE_KERNEL_LZO
79 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
80 select HAVE_KRETPROBES if (HAVE_KPROBES)
82 select HAVE_MOD_ARCH_SPECIFIC
84 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
85 select HAVE_OPTPROBES if !THUMB2_KERNEL
86 select HAVE_PERF_EVENTS
88 select HAVE_PERF_USER_STACK_DUMP
89 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
90 select HAVE_REGS_AND_STACK_ACCESS_API
91 select HAVE_SYSCALL_TRACEPOINTS
93 select HAVE_VIRT_CPU_ACCOUNTING_GEN
94 select IRQ_FORCED_THREADING
95 select MODULES_USE_ELF_REL
97 select OF_EARLY_FLATTREE if OF
98 select OF_RESERVED_MEM if OF
100 select OLD_SIGSUSPEND3
101 select PERF_USE_VMALLOC
103 select SYS_SUPPORTS_APM_EMULATION
104 # Above selects are sorted alphabetically; please add new ones
105 # according to that. Thanks.
107 The ARM series is a line of low-power-consumption RISC chip designs
108 licensed by ARM Ltd and targeted at embedded applications and
109 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
110 manufactured, but legacy ARM-based PC hardware remains popular in
111 Europe. There is an ARM Linux project with a web page at
112 <http://www.arm.linux.org.uk/>.
114 config ARM_HAS_SG_CHAIN
115 select ARCH_HAS_SG_CHAIN
118 config NEED_SG_DMA_LENGTH
121 config ARM_DMA_USE_IOMMU
123 select ARM_HAS_SG_CHAIN
124 select NEED_SG_DMA_LENGTH
128 config ARM_DMA_IOMMU_ALIGNMENT
129 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
133 DMA mapping framework by default aligns all buffers to the smallest
134 PAGE_SIZE order which is greater than or equal to the requested buffer
135 size. This works well for buffers up to a few hundreds kilobytes, but
136 for larger buffers it just a waste of address space. Drivers which has
137 relatively small addressing window (like 64Mib) might run out of
138 virtual space with just a few allocations.
140 With this parameter you can specify the maximum PAGE_SIZE order for
141 DMA IOMMU buffers. Larger buffers will be aligned only to this
142 specified order. The order is expressed as a power of two multiplied
147 config MIGHT_HAVE_PCI
150 config SYS_SUPPORTS_APM_EMULATION
155 select GENERIC_ALLOCATOR
166 The Extended Industry Standard Architecture (EISA) bus was
167 developed as an open alternative to the IBM MicroChannel bus.
169 The EISA bus provided some of the features of the IBM MicroChannel
170 bus while maintaining backward compatibility with cards made for
171 the older ISA bus. The EISA bus saw limited use between 1988 and
172 1995 when it was made obsolete by the PCI bus.
174 Say Y here if you are building a kernel for an EISA-based machine.
181 config STACKTRACE_SUPPORT
185 config LOCKDEP_SUPPORT
189 config TRACE_IRQFLAGS_SUPPORT
193 config RWSEM_XCHGADD_ALGORITHM
197 config ARCH_HAS_ILOG2_U32
200 config ARCH_HAS_ILOG2_U64
203 config ARCH_HAS_BANDGAP
206 config FIX_EARLYCON_MEM
209 config GENERIC_HWEIGHT
213 config GENERIC_CALIBRATE_DELAY
217 config ARCH_MAY_HAVE_PC_FDC
223 config NEED_DMA_MAP_STATE
226 config ARCH_SUPPORTS_UPROBES
229 config ARCH_HAS_DMA_SET_COHERENT_MASK
232 config GENERIC_ISA_DMA
238 config NEED_RET_TO_USER
246 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
247 default DRAM_BASE if REMAP_VECTORS_TO_RAM
250 The base address of exception vectors. This must be two pages
253 config ARM_PATCH_PHYS_VIRT
254 bool "Patch physical to virtual translations at runtime" if EMBEDDED
256 depends on !XIP_KERNEL && MMU
258 Patch phys-to-virt and virt-to-phys translation functions at
259 boot and module load time according to the position of the
260 kernel in system memory.
262 This can only be used with non-XIP MMU kernels where the base
263 of physical memory is at a 16MB boundary.
265 Only disable this option if you know that you do not require
266 this feature (eg, building a kernel for a single machine) and
267 you need to shrink the kernel to the minimal size.
269 config NEED_MACH_IO_H
272 Select this when mach/io.h is required to provide special
273 definitions for this platform. The need for mach/io.h should
274 be avoided when possible.
276 config NEED_MACH_MEMORY_H
279 Select this when mach/memory.h is required to provide special
280 definitions for this platform. The need for mach/memory.h should
281 be avoided when possible.
284 hex "Physical address of main memory" if MMU
285 depends on !ARM_PATCH_PHYS_VIRT
286 default DRAM_BASE if !MMU
287 default 0x00000000 if ARCH_EBSA110 || \
293 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
294 default 0x20000000 if ARCH_S5PV210
295 default 0xc0000000 if ARCH_SA1100
297 Please provide the physical address corresponding to the
298 location of main memory in your system.
304 config PGTABLE_LEVELS
306 default 3 if ARM_LPAE
309 source "init/Kconfig"
311 source "kernel/Kconfig.freezer"
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
320 support by paged memory management. If unsure, say 'Y'.
322 config ARCH_MMAP_RND_BITS_MIN
325 config ARCH_MMAP_RND_BITS_MAX
326 default 14 if PAGE_OFFSET=0x40000000
327 default 15 if PAGE_OFFSET=0x80000000
331 # The "ARM system type" choice list is ordered alphabetically by option
332 # text. Please add new entries in the option alphabetic order.
335 prompt "ARM system type"
336 default ARM_SINGLE_ARMV7M if !MMU
337 default ARCH_MULTIPLATFORM if MMU
339 config ARCH_MULTIPLATFORM
340 bool "Allow multiple platforms to be selected"
342 select ARM_HAS_SG_CHAIN
343 select ARM_PATCH_PHYS_VIRT
347 select GENERIC_CLOCKEVENTS
348 select MIGHT_HAVE_PCI
349 select MULTI_IRQ_HANDLER
350 select PCI_DOMAINS if PCI
354 config ARM_SINGLE_ARMV7M
355 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
362 select GENERIC_CLOCKEVENTS
369 select ARCH_USES_GETTIMEOFFSET
372 select NEED_MACH_IO_H
373 select NEED_MACH_MEMORY_H
376 This is an evaluation board for the StrongARM processor available
377 from Digital. It has limited hardware on-board, including an
378 Ethernet interface, two PCMCIA sockets, two serial ports and a
383 select ARCH_HAS_HOLES_MEMORYMODEL
385 imply ARM_PATCH_PHYS_VIRT
391 select GENERIC_CLOCKEVENTS
394 This enables support for the Cirrus EP93xx series of CPUs.
396 config ARCH_FOOTBRIDGE
400 select GENERIC_CLOCKEVENTS
402 select NEED_MACH_IO_H if !MMU
403 select NEED_MACH_MEMORY_H
405 Support for systems based on the DC21285 companion chip
406 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
409 bool "Hilscher NetX based"
413 select GENERIC_CLOCKEVENTS
415 This enables support for systems based on the Hilscher NetX Soc
421 select NEED_MACH_MEMORY_H
422 select NEED_RET_TO_USER
428 Support for Intel's IOP13XX (XScale) family of processors.
436 select NEED_RET_TO_USER
440 Support for Intel's 80219 and IOP32X (XScale) family of
449 select NEED_RET_TO_USER
453 Support for Intel's IOP33X (XScale) family of processors.
458 select ARCH_HAS_DMA_SET_COHERENT_MASK
459 select ARCH_SUPPORTS_BIG_ENDIAN
462 select DMABOUNCE if PCI
463 select GENERIC_CLOCKEVENTS
465 select MIGHT_HAVE_PCI
466 select NEED_MACH_IO_H
467 select USB_EHCI_BIG_ENDIAN_DESC
468 select USB_EHCI_BIG_ENDIAN_MMIO
470 Support for Intel's IXP4XX (XScale) family of processors.
475 select GENERIC_CLOCKEVENTS
477 select MIGHT_HAVE_PCI
478 select MULTI_IRQ_HANDLER
482 select PLAT_ORION_LEGACY
484 select PM_GENERIC_DOMAINS if PM
486 Support for the Marvell Dove SoC 88AP510
489 bool "Micrel/Kendin KS8695"
492 select GENERIC_CLOCKEVENTS
494 select NEED_MACH_MEMORY_H
496 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
497 System-on-Chip devices.
500 bool "Nuvoton W90X900 CPU"
504 select GENERIC_CLOCKEVENTS
507 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
508 At present, the w90x900 has been renamed nuc900, regarding
509 the ARM series product line, you can login the following
510 link address to know more.
512 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
513 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
519 select CLKSRC_LPC32XX
522 select GENERIC_CLOCKEVENTS
524 select MULTI_IRQ_HANDLER
528 Support for the NXP LPC32XX family of processors
531 bool "PXA2xx/PXA3xx-based"
534 select ARM_CPU_SUSPEND if PM
541 select CPU_XSCALE if !CPU_XSC3
542 select GENERIC_CLOCKEVENTS
547 select MULTI_IRQ_HANDLER
551 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
557 select ARCH_MAY_HAVE_PC_FDC
558 select ARCH_SPARSEMEM_ENABLE
559 select ARCH_USES_GETTIMEOFFSET
563 select HAVE_PATA_PLATFORM
565 select NEED_MACH_IO_H
566 select NEED_MACH_MEMORY_H
569 On the Acorn Risc-PC, Linux can support the internal IDE disk and
570 CD-ROM interface, serial and parallel port, and the floppy drive.
575 select ARCH_SPARSEMEM_ENABLE
579 select TIMER_OF if OF
582 select GENERIC_CLOCKEVENTS
587 select MULTI_IRQ_HANDLER
588 select NEED_MACH_MEMORY_H
591 Support for StrongARM 11x0 based boards.
594 bool "Samsung S3C24XX SoCs"
597 select CLKSRC_SAMSUNG_PWM
598 select GENERIC_CLOCKEVENTS
601 select HAVE_S3C2410_I2C if I2C
602 select HAVE_S3C2410_WATCHDOG if WATCHDOG
603 select HAVE_S3C_RTC if RTC_CLASS
604 select MULTI_IRQ_HANDLER
605 select NEED_MACH_IO_H
606 select S3C2410_WATCHDOG
610 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
611 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
612 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
613 Samsung SMDK2410 development board (and derivatives).
617 select ARCH_HAS_HOLES_MEMORYMODEL
620 select GENERIC_ALLOCATOR
621 select GENERIC_CLOCKEVENTS
622 select GENERIC_IRQ_CHIP
628 Support for TI's DaVinci platform.
633 select ARCH_HAS_HOLES_MEMORYMODEL
637 select GENERIC_CLOCKEVENTS
638 select GENERIC_IRQ_CHIP
642 select MULTI_IRQ_HANDLER
643 select NEED_MACH_IO_H if PCCARD
644 select NEED_MACH_MEMORY_H
647 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
651 menu "Multiple platform selection"
652 depends on ARCH_MULTIPLATFORM
654 comment "CPU Core family selection"
657 bool "ARMv4 based platforms (FA526)"
658 depends on !ARCH_MULTI_V6_V7
659 select ARCH_MULTI_V4_V5
662 config ARCH_MULTI_V4T
663 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
664 depends on !ARCH_MULTI_V6_V7
665 select ARCH_MULTI_V4_V5
666 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
667 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
668 CPU_ARM925T || CPU_ARM940T)
671 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
672 depends on !ARCH_MULTI_V6_V7
673 select ARCH_MULTI_V4_V5
674 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
675 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
676 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
678 config ARCH_MULTI_V4_V5
682 bool "ARMv6 based platforms (ARM11)"
683 select ARCH_MULTI_V6_V7
687 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
689 select ARCH_MULTI_V6_V7
693 config ARCH_MULTI_V6_V7
695 select MIGHT_HAVE_CACHE_L2X0
697 config ARCH_MULTI_CPU_AUTO
698 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
704 bool "Dummy Virtual Machine"
705 depends on ARCH_MULTI_V7
708 select ARM_GIC_V2M if PCI
710 select ARM_GIC_V3_ITS if PCI
712 select HAVE_ARM_ARCH_TIMER
715 # This is sorted alphabetically by mach-* pathname. However, plat-*
716 # Kconfigs may be included either alphabetically (according to the
717 # plat- suffix) or along side the corresponding mach-* source.
719 source "arch/arm/mach-mvebu/Kconfig"
721 source "arch/arm/mach-actions/Kconfig"
723 source "arch/arm/mach-alpine/Kconfig"
725 source "arch/arm/mach-artpec/Kconfig"
727 source "arch/arm/mach-asm9260/Kconfig"
729 source "arch/arm/mach-at91/Kconfig"
731 source "arch/arm/mach-axxia/Kconfig"
733 source "arch/arm/mach-bcm/Kconfig"
735 source "arch/arm/mach-berlin/Kconfig"
737 source "arch/arm/mach-clps711x/Kconfig"
739 source "arch/arm/mach-cns3xxx/Kconfig"
741 source "arch/arm/mach-davinci/Kconfig"
743 source "arch/arm/mach-digicolor/Kconfig"
745 source "arch/arm/mach-dove/Kconfig"
747 source "arch/arm/mach-ep93xx/Kconfig"
749 source "arch/arm/mach-footbridge/Kconfig"
751 source "arch/arm/mach-gemini/Kconfig"
753 source "arch/arm/mach-highbank/Kconfig"
755 source "arch/arm/mach-hisi/Kconfig"
757 source "arch/arm/mach-integrator/Kconfig"
759 source "arch/arm/mach-iop32x/Kconfig"
761 source "arch/arm/mach-iop33x/Kconfig"
763 source "arch/arm/mach-iop13xx/Kconfig"
765 source "arch/arm/mach-ixp4xx/Kconfig"
767 source "arch/arm/mach-keystone/Kconfig"
769 source "arch/arm/mach-ks8695/Kconfig"
771 source "arch/arm/mach-meson/Kconfig"
773 source "arch/arm/mach-moxart/Kconfig"
775 source "arch/arm/mach-aspeed/Kconfig"
777 source "arch/arm/mach-mv78xx0/Kconfig"
779 source "arch/arm/mach-imx/Kconfig"
781 source "arch/arm/mach-mediatek/Kconfig"
783 source "arch/arm/mach-mxs/Kconfig"
785 source "arch/arm/mach-netx/Kconfig"
787 source "arch/arm/mach-nomadik/Kconfig"
789 source "arch/arm/mach-nspire/Kconfig"
791 source "arch/arm/plat-omap/Kconfig"
793 source "arch/arm/mach-omap1/Kconfig"
795 source "arch/arm/mach-omap2/Kconfig"
797 source "arch/arm/mach-orion5x/Kconfig"
799 source "arch/arm/mach-picoxcell/Kconfig"
801 source "arch/arm/mach-pxa/Kconfig"
802 source "arch/arm/plat-pxa/Kconfig"
804 source "arch/arm/mach-mmp/Kconfig"
806 source "arch/arm/mach-oxnas/Kconfig"
808 source "arch/arm/mach-qcom/Kconfig"
810 source "arch/arm/mach-realview/Kconfig"
812 source "arch/arm/mach-rockchip/Kconfig"
814 source "arch/arm/mach-sa1100/Kconfig"
816 source "arch/arm/mach-socfpga/Kconfig"
818 source "arch/arm/mach-spear/Kconfig"
820 source "arch/arm/mach-sti/Kconfig"
822 source "arch/arm/mach-stm32/Kconfig"
824 source "arch/arm/mach-s3c24xx/Kconfig"
826 source "arch/arm/mach-s3c64xx/Kconfig"
828 source "arch/arm/mach-s5pv210/Kconfig"
830 source "arch/arm/mach-exynos/Kconfig"
831 source "arch/arm/plat-samsung/Kconfig"
833 source "arch/arm/mach-shmobile/Kconfig"
835 source "arch/arm/mach-sunxi/Kconfig"
837 source "arch/arm/mach-prima2/Kconfig"
839 source "arch/arm/mach-tango/Kconfig"
841 source "arch/arm/mach-tegra/Kconfig"
843 source "arch/arm/mach-u300/Kconfig"
845 source "arch/arm/mach-uniphier/Kconfig"
847 source "arch/arm/mach-ux500/Kconfig"
849 source "arch/arm/mach-versatile/Kconfig"
851 source "arch/arm/mach-vexpress/Kconfig"
852 source "arch/arm/plat-versatile/Kconfig"
854 source "arch/arm/mach-vt8500/Kconfig"
856 source "arch/arm/mach-w90x900/Kconfig"
858 source "arch/arm/mach-zx/Kconfig"
860 source "arch/arm/mach-zynq/Kconfig"
862 # ARMv7-M architecture
864 bool "Energy Micro efm32"
865 depends on ARM_SINGLE_ARMV7M
868 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
872 bool "NXP LPC18xx/LPC43xx"
873 depends on ARM_SINGLE_ARMV7M
874 select ARCH_HAS_RESET_CONTROLLER
876 select CLKSRC_LPC32XX
879 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
880 high performance microcontrollers.
883 bool "ARM MPS2 platform"
884 depends on ARM_SINGLE_ARMV7M
888 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
889 with a range of available cores like Cortex-M3/M4/M7.
891 Please, note that depends which Application Note is used memory map
892 for the platform may vary, so adjustment of RAM base might be needed.
894 # Definitions to make life easier
900 select GENERIC_CLOCKEVENTS
906 select GENERIC_IRQ_CHIP
909 config PLAT_ORION_LEGACY
916 config PLAT_VERSATILE
919 source "arch/arm/firmware/Kconfig"
921 source arch/arm/mm/Kconfig
924 bool "Enable iWMMXt support"
925 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
926 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
928 Enable support for iWMMXt context switching at run time if
929 running on a CPU that supports it.
931 config MULTI_IRQ_HANDLER
934 Allow each machine to specify it's own IRQ handler at run time.
937 source "arch/arm/Kconfig-nommu"
940 config PJ4B_ERRATA_4742
941 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
942 depends on CPU_PJ4B && MACH_ARMADA_370
945 When coming out of either a Wait for Interrupt (WFI) or a Wait for
946 Event (WFE) IDLE states, a specific timing sensitivity exists between
947 the retiring WFI/WFE instructions and the newly issued subsequent
948 instructions. This sensitivity can result in a CPU hang scenario.
950 The software must insert either a Data Synchronization Barrier (DSB)
951 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
954 config ARM_ERRATA_326103
955 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
958 Executing a SWP instruction to read-only memory does not set bit 11
959 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
960 treat the access as a read, preventing a COW from occurring and
961 causing the faulting task to livelock.
963 config ARM_ERRATA_411920
964 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
965 depends on CPU_V6 || CPU_V6K
967 Invalidation of the Instruction Cache operation can
968 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
969 It does not affect the MPCore. This option enables the ARM Ltd.
970 recommended workaround.
972 config ARM_ERRATA_430973
973 bool "ARM errata: Stale prediction on replaced interworking branch"
976 This option enables the workaround for the 430973 Cortex-A8
977 r1p* erratum. If a code sequence containing an ARM/Thumb
978 interworking branch is replaced with another code sequence at the
979 same virtual address, whether due to self-modifying code or virtual
980 to physical address re-mapping, Cortex-A8 does not recover from the
981 stale interworking branch prediction. This results in Cortex-A8
982 executing the new code sequence in the incorrect ARM or Thumb state.
983 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
984 and also flushes the branch target cache at every context switch.
985 Note that setting specific bits in the ACTLR register may not be
986 available in non-secure mode.
988 config ARM_ERRATA_458693
989 bool "ARM errata: Processor deadlock when a false hazard is created"
991 depends on !ARCH_MULTIPLATFORM
993 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
994 erratum. For very specific sequences of memory operations, it is
995 possible for a hazard condition intended for a cache line to instead
996 be incorrectly associated with a different cache line. This false
997 hazard might then cause a processor deadlock. The workaround enables
998 the L1 caching of the NEON accesses and disables the PLD instruction
999 in the ACTLR register. Note that setting specific bits in the ACTLR
1000 register may not be available in non-secure mode.
1002 config ARM_ERRATA_460075
1003 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1005 depends on !ARCH_MULTIPLATFORM
1007 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1008 erratum. Any asynchronous access to the L2 cache may encounter a
1009 situation in which recent store transactions to the L2 cache are lost
1010 and overwritten with stale memory contents from external memory. The
1011 workaround disables the write-allocate mode for the L2 cache via the
1012 ACTLR register. Note that setting specific bits in the ACTLR register
1013 may not be available in non-secure mode.
1015 config ARM_ERRATA_742230
1016 bool "ARM errata: DMB operation may be faulty"
1017 depends on CPU_V7 && SMP
1018 depends on !ARCH_MULTIPLATFORM
1020 This option enables the workaround for the 742230 Cortex-A9
1021 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1022 between two write operations may not ensure the correct visibility
1023 ordering of the two writes. This workaround sets a specific bit in
1024 the diagnostic register of the Cortex-A9 which causes the DMB
1025 instruction to behave as a DSB, ensuring the correct behaviour of
1028 config ARM_ERRATA_742231
1029 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1030 depends on CPU_V7 && SMP
1031 depends on !ARCH_MULTIPLATFORM
1033 This option enables the workaround for the 742231 Cortex-A9
1034 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1035 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1036 accessing some data located in the same cache line, may get corrupted
1037 data due to bad handling of the address hazard when the line gets
1038 replaced from one of the CPUs at the same time as another CPU is
1039 accessing it. This workaround sets specific bits in the diagnostic
1040 register of the Cortex-A9 which reduces the linefill issuing
1041 capabilities of the processor.
1043 config ARM_ERRATA_643719
1044 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1045 depends on CPU_V7 && SMP
1048 This option enables the workaround for the 643719 Cortex-A9 (prior to
1049 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1050 register returns zero when it should return one. The workaround
1051 corrects this value, ensuring cache maintenance operations which use
1052 it behave as intended and avoiding data corruption.
1054 config ARM_ERRATA_720789
1055 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1058 This option enables the workaround for the 720789 Cortex-A9 (prior to
1059 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1060 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1061 As a consequence of this erratum, some TLB entries which should be
1062 invalidated are not, resulting in an incoherency in the system page
1063 tables. The workaround changes the TLB flushing routines to invalidate
1064 entries regardless of the ASID.
1066 config ARM_ERRATA_743622
1067 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1069 depends on !ARCH_MULTIPLATFORM
1071 This option enables the workaround for the 743622 Cortex-A9
1072 (r2p*) erratum. Under very rare conditions, a faulty
1073 optimisation in the Cortex-A9 Store Buffer may lead to data
1074 corruption. This workaround sets a specific bit in the diagnostic
1075 register of the Cortex-A9 which disables the Store Buffer
1076 optimisation, preventing the defect from occurring. This has no
1077 visible impact on the overall performance or power consumption of the
1080 config ARM_ERRATA_751472
1081 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1083 depends on !ARCH_MULTIPLATFORM
1085 This option enables the workaround for the 751472 Cortex-A9 (prior
1086 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1087 completion of a following broadcasted operation if the second
1088 operation is received by a CPU before the ICIALLUIS has completed,
1089 potentially leading to corrupted entries in the cache or TLB.
1091 config ARM_ERRATA_754322
1092 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1095 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1096 r3p*) erratum. A speculative memory access may cause a page table walk
1097 which starts prior to an ASID switch but completes afterwards. This
1098 can populate the micro-TLB with a stale entry which may be hit with
1099 the new ASID. This workaround places two dsb instructions in the mm
1100 switching code so that no page table walks can cross the ASID switch.
1102 config ARM_ERRATA_754327
1103 bool "ARM errata: no automatic Store Buffer drain"
1104 depends on CPU_V7 && SMP
1106 This option enables the workaround for the 754327 Cortex-A9 (prior to
1107 r2p0) erratum. The Store Buffer does not have any automatic draining
1108 mechanism and therefore a livelock may occur if an external agent
1109 continuously polls a memory location waiting to observe an update.
1110 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1111 written polling loops from denying visibility of updates to memory.
1113 config ARM_ERRATA_364296
1114 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1117 This options enables the workaround for the 364296 ARM1136
1118 r0p2 erratum (possible cache data corruption with
1119 hit-under-miss enabled). It sets the undocumented bit 31 in
1120 the auxiliary control register and the FI bit in the control
1121 register, thus disabling hit-under-miss without putting the
1122 processor into full low interrupt latency mode. ARM11MPCore
1125 config ARM_ERRATA_764369
1126 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1127 depends on CPU_V7 && SMP
1129 This option enables the workaround for erratum 764369
1130 affecting Cortex-A9 MPCore with two or more processors (all
1131 current revisions). Under certain timing circumstances, a data
1132 cache line maintenance operation by MVA targeting an Inner
1133 Shareable memory region may fail to proceed up to either the
1134 Point of Coherency or to the Point of Unification of the
1135 system. This workaround adds a DSB instruction before the
1136 relevant cache maintenance functions and sets a specific bit
1137 in the diagnostic control register of the SCU.
1139 config ARM_ERRATA_775420
1140 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1143 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1144 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1145 operation aborts with MMU exception, it might cause the processor
1146 to deadlock. This workaround puts DSB before executing ISB if
1147 an abort may occur on cache maintenance.
1149 config ARM_ERRATA_798181
1150 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1151 depends on CPU_V7 && SMP
1153 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1154 adequately shooting down all use of the old entries. This
1155 option enables the Linux kernel workaround for this erratum
1156 which sends an IPI to the CPUs that are running the same ASID
1157 as the one being invalidated.
1159 config ARM_ERRATA_773022
1160 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1163 This option enables the workaround for the 773022 Cortex-A15
1164 (up to r0p4) erratum. In certain rare sequences of code, the
1165 loop buffer may deliver incorrect instructions. This
1166 workaround disables the loop buffer to avoid the erratum.
1168 config ARM_ERRATA_818325_852422
1169 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1172 This option enables the workaround for:
1173 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1174 instruction might deadlock. Fixed in r0p1.
1175 - Cortex-A12 852422: Execution of a sequence of instructions might
1176 lead to either a data corruption or a CPU deadlock. Not fixed in
1177 any Cortex-A12 cores yet.
1178 This workaround for all both errata involves setting bit[12] of the
1179 Feature Register. This bit disables an optimisation applied to a
1180 sequence of 2 instructions that use opposing condition codes.
1182 config ARM_ERRATA_821420
1183 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1186 This option enables the workaround for the 821420 Cortex-A12
1187 (all revs) erratum. In very rare timing conditions, a sequence
1188 of VMOV to Core registers instructions, for which the second
1189 one is in the shadow of a branch or abort, can lead to a
1190 deadlock when the VMOV instructions are issued out-of-order.
1192 config ARM_ERRATA_825619
1193 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1196 This option enables the workaround for the 825619 Cortex-A12
1197 (all revs) erratum. Within rare timing constraints, executing a
1198 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1199 and Device/Strongly-Ordered loads and stores might cause deadlock
1201 config ARM_ERRATA_852421
1202 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1205 This option enables the workaround for the 852421 Cortex-A17
1206 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1207 execution of a DMB ST instruction might fail to properly order
1208 stores from GroupA and stores from GroupB.
1210 config ARM_ERRATA_852423
1211 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1214 This option enables the workaround for:
1215 - Cortex-A17 852423: Execution of a sequence of instructions might
1216 lead to either a data corruption or a CPU deadlock. Not fixed in
1217 any Cortex-A17 cores yet.
1218 This is identical to Cortex-A12 erratum 852422. It is a separate
1219 config option from the A12 erratum due to the way errata are checked
1224 source "arch/arm/common/Kconfig"
1231 Find out whether you have ISA slots on your motherboard. ISA is the
1232 name of a bus system, i.e. the way the CPU talks to the other stuff
1233 inside your box. Other bus systems are PCI, EISA, MicroChannel
1234 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1235 newer boards don't support it. If you have ISA, say Y, otherwise N.
1237 # Select ISA DMA controller support
1242 # Select ISA DMA interface
1247 bool "PCI support" if MIGHT_HAVE_PCI
1249 Find out whether you have a PCI motherboard. PCI is the name of a
1250 bus system, i.e. the way the CPU talks to the other stuff inside
1251 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1252 VESA. If you have PCI, say Y, otherwise N.
1258 config PCI_DOMAINS_GENERIC
1259 def_bool PCI_DOMAINS
1261 config PCI_NANOENGINE
1262 bool "BSE nanoEngine PCI support"
1263 depends on SA1100_NANOENGINE
1265 Enable PCI on the BSE nanoEngine board.
1270 config PCI_HOST_ITE8152
1272 depends on PCI && MACH_ARMCORE
1276 source "drivers/pci/Kconfig"
1278 source "drivers/pcmcia/Kconfig"
1282 menu "Kernel Features"
1287 This option should be selected by machines which have an SMP-
1290 The only effect of this option is to make the SMP-related
1291 options available to the user for configuration.
1294 bool "Symmetric Multi-Processing"
1295 depends on CPU_V6K || CPU_V7
1296 depends on GENERIC_CLOCKEVENTS
1298 depends on MMU || ARM_MPU
1301 This enables support for systems with more than one CPU. If you have
1302 a system with only one CPU, say N. If you have a system with more
1303 than one CPU, say Y.
1305 If you say N here, the kernel will run on uni- and multiprocessor
1306 machines, but will use only one CPU of a multiprocessor machine. If
1307 you say Y here, the kernel will run on many, but not all,
1308 uniprocessor machines. On a uniprocessor machine, the kernel
1309 will run faster if you say N here.
1311 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1312 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1313 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1315 If you don't know what to do here, say N.
1318 bool "Allow booting SMP kernel on uniprocessor systems"
1319 depends on SMP && !XIP_KERNEL && MMU
1322 SMP kernels contain instructions which fail on non-SMP processors.
1323 Enabling this option allows the kernel to modify itself to make
1324 these instructions safe. Disabling it allows about 1K of space
1327 If you don't know what to do here, say Y.
1329 config ARM_CPU_TOPOLOGY
1330 bool "Support cpu topology definition"
1331 depends on SMP && CPU_V7
1334 Support ARM cpu topology definition. The MPIDR register defines
1335 affinity between processors which is then used to describe the cpu
1336 topology of an ARM System.
1339 bool "Multi-core scheduler support"
1340 depends on ARM_CPU_TOPOLOGY
1342 Multi-core scheduler support improves the CPU scheduler's decision
1343 making when dealing with multi-core CPU chips at a cost of slightly
1344 increased overhead in some places. If unsure say N here.
1347 bool "SMT scheduler support"
1348 depends on ARM_CPU_TOPOLOGY
1350 Improves the CPU scheduler's decision making when dealing with
1351 MultiThreading at a cost of slightly increased overhead in some
1352 places. If unsure say N here.
1357 This option enables support for the ARM system coherency unit
1359 config HAVE_ARM_ARCH_TIMER
1360 bool "Architected timer support"
1362 select ARM_ARCH_TIMER
1363 select GENERIC_CLOCKEVENTS
1365 This option enables support for the ARM architected timer
1369 select TIMER_OF if OF
1371 This options enables support for the ARM timer and watchdog unit
1374 bool "Multi-Cluster Power Management"
1375 depends on CPU_V7 && SMP
1377 This option provides the common power management infrastructure
1378 for (multi-)cluster based systems, such as big.LITTLE based
1381 config MCPM_QUAD_CLUSTER
1385 To avoid wasting resources unnecessarily, MCPM only supports up
1386 to 2 clusters by default.
1387 Platforms with 3 or 4 clusters that use MCPM must select this
1388 option to allow the additional clusters to be managed.
1391 bool "big.LITTLE support (Experimental)"
1392 depends on CPU_V7 && SMP
1395 This option enables support selections for the big.LITTLE
1396 system architecture.
1399 bool "big.LITTLE switcher support"
1400 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1403 The big.LITTLE "switcher" provides the core functionality to
1404 transparently handle transition between a cluster of A15's
1405 and a cluster of A7's in a big.LITTLE system.
1407 config BL_SWITCHER_DUMMY_IF
1408 tristate "Simple big.LITTLE switcher user interface"
1409 depends on BL_SWITCHER && DEBUG_KERNEL
1411 This is a simple and dummy char dev interface to control
1412 the big.LITTLE switcher core code. It is meant for
1413 debugging purposes only.
1416 prompt "Memory split"
1420 Select the desired split between kernel and user memory.
1422 If you are not absolutely sure what you are doing, leave this
1426 bool "3G/1G user/kernel split"
1427 config VMSPLIT_3G_OPT
1428 depends on !ARM_LPAE
1429 bool "3G/1G user/kernel split (for full 1G low memory)"
1431 bool "2G/2G user/kernel split"
1433 bool "1G/3G user/kernel split"
1438 default PHYS_OFFSET if !MMU
1439 default 0x40000000 if VMSPLIT_1G
1440 default 0x80000000 if VMSPLIT_2G
1441 default 0xB0000000 if VMSPLIT_3G_OPT
1445 int "Maximum number of CPUs (2-32)"
1451 bool "Support for hot-pluggable CPUs"
1453 select GENERIC_IRQ_MIGRATION
1455 Say Y here to experiment with turning CPUs off and on. CPUs
1456 can be controlled through /sys/devices/system/cpu.
1459 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1460 depends on HAVE_ARM_SMCCC
1463 Say Y here if you want Linux to communicate with system firmware
1464 implementing the PSCI specification for CPU-centric power
1465 management operations described in ARM document number ARM DEN
1466 0022A ("Power State Coordination Interface System Software on
1469 # The GPIO number here must be sorted by descending number. In case of
1470 # a multiplatform kernel, we just want the highest value required by the
1471 # selected platforms.
1474 default 2048 if ARCH_SOCFPGA
1475 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1477 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1478 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1479 default 416 if ARCH_SUNXI
1480 default 392 if ARCH_U8500
1481 default 352 if ARCH_VT8500
1482 default 288 if ARCH_ROCKCHIP
1483 default 264 if MACH_H4700
1486 Maximum number of GPIOs in the system.
1488 If unsure, leave the default value.
1490 source kernel/Kconfig.preempt
1494 default 200 if ARCH_EBSA110
1495 default 128 if SOC_AT91RM9200
1499 depends on HZ_FIXED = 0
1500 prompt "Timer frequency"
1524 default HZ_FIXED if HZ_FIXED != 0
1525 default 100 if HZ_100
1526 default 200 if HZ_200
1527 default 250 if HZ_250
1528 default 300 if HZ_300
1529 default 500 if HZ_500
1533 def_bool HIGH_RES_TIMERS
1535 config THUMB2_KERNEL
1536 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1537 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1538 default y if CPU_THUMBONLY
1541 By enabling this option, the kernel will be compiled in
1546 config THUMB2_AVOID_R_ARM_THM_JUMP11
1547 bool "Work around buggy Thumb-2 short branch relocations in gas"
1548 depends on THUMB2_KERNEL && MODULES
1551 Various binutils versions can resolve Thumb-2 branches to
1552 locally-defined, preemptible global symbols as short-range "b.n"
1553 branch instructions.
1555 This is a problem, because there's no guarantee the final
1556 destination of the symbol, or any candidate locations for a
1557 trampoline, are within range of the branch. For this reason, the
1558 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1559 relocation in modules at all, and it makes little sense to add
1562 The symptom is that the kernel fails with an "unsupported
1563 relocation" error when loading some modules.
1565 Until fixed tools are available, passing
1566 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1567 code which hits this problem, at the cost of a bit of extra runtime
1568 stack usage in some cases.
1570 The problem is described in more detail at:
1571 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1573 Only Thumb-2 kernels are affected.
1575 Unless you are sure your tools don't have this problem, say Y.
1577 config ARM_PATCH_IDIV
1578 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1579 depends on CPU_32v7 && !XIP_KERNEL
1582 The ARM compiler inserts calls to __aeabi_idiv() and
1583 __aeabi_uidiv() when it needs to perform division on signed
1584 and unsigned integers. Some v7 CPUs have support for the sdiv
1585 and udiv instructions that can be used to implement those
1588 Enabling this option allows the kernel to modify itself to
1589 replace the first two instructions of these library functions
1590 with the sdiv or udiv plus "bx lr" instructions when the CPU
1591 it is running on supports them. Typically this will be faster
1592 and less power intensive than running the original library
1593 code to do integer division.
1596 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1597 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1599 This option allows for the kernel to be compiled using the latest
1600 ARM ABI (aka EABI). This is only useful if you are using a user
1601 space environment that is also compiled with EABI.
1603 Since there are major incompatibilities between the legacy ABI and
1604 EABI, especially with regard to structure member alignment, this
1605 option also changes the kernel syscall calling convention to
1606 disambiguate both ABIs and allow for backward compatibility support
1607 (selected with CONFIG_OABI_COMPAT).
1609 To use this you need GCC version 4.0.0 or later.
1612 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1613 depends on AEABI && !THUMB2_KERNEL
1615 This option preserves the old syscall interface along with the
1616 new (ARM EABI) one. It also provides a compatibility layer to
1617 intercept syscalls that have structure arguments which layout
1618 in memory differs between the legacy ABI and the new ARM EABI
1619 (only for non "thumb" binaries). This option adds a tiny
1620 overhead to all syscalls and produces a slightly larger kernel.
1622 The seccomp filter system will not be available when this is
1623 selected, since there is no way yet to sensibly distinguish
1624 between calling conventions during filtering.
1626 If you know you'll be using only pure EABI user space then you
1627 can say N here. If this option is not selected and you attempt
1628 to execute a legacy ABI binary then the result will be
1629 UNPREDICTABLE (in fact it can be predicted that it won't work
1630 at all). If in doubt say N.
1632 config ARCH_HAS_HOLES_MEMORYMODEL
1635 config ARCH_SPARSEMEM_ENABLE
1638 config ARCH_SPARSEMEM_DEFAULT
1639 def_bool ARCH_SPARSEMEM_ENABLE
1641 config ARCH_SELECT_MEMORY_MODEL
1642 def_bool ARCH_SPARSEMEM_ENABLE
1644 config HAVE_ARCH_PFN_VALID
1645 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1647 config HAVE_GENERIC_GUP
1652 bool "High Memory Support"
1655 The address space of ARM processors is only 4 Gigabytes large
1656 and it has to accommodate user address space, kernel address
1657 space as well as some memory mapped IO. That means that, if you
1658 have a large amount of physical memory and/or IO, not all of the
1659 memory can be "permanently mapped" by the kernel. The physical
1660 memory that is not permanently mapped is called "high memory".
1662 Depending on the selected kernel/user memory split, minimum
1663 vmalloc space and actual amount of RAM, you may not need this
1664 option which should result in a slightly faster kernel.
1669 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1673 The VM uses one page of physical memory for each page table.
1674 For systems with a lot of processes, this can use a lot of
1675 precious low memory, eventually leading to low memory being
1676 consumed by page tables. Setting this option will allow
1677 user-space 2nd level page tables to reside in high memory.
1679 config CPU_SW_DOMAIN_PAN
1680 bool "Enable use of CPU domains to implement privileged no-access"
1681 depends on MMU && !ARM_LPAE
1684 Increase kernel security by ensuring that normal kernel accesses
1685 are unable to access userspace addresses. This can help prevent
1686 use-after-free bugs becoming an exploitable privilege escalation
1687 by ensuring that magic values (such as LIST_POISON) will always
1688 fault when dereferenced.
1690 CPUs with low-vector mappings use a best-efforts implementation.
1691 Their lower 1MB needs to remain accessible for the vectors, but
1692 the remainder of userspace will become appropriately inaccessible.
1694 config HW_PERF_EVENTS
1698 config SYS_SUPPORTS_HUGETLBFS
1702 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1706 config ARCH_WANT_GENERAL_HUGETLB
1709 config ARM_MODULE_PLTS
1710 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1713 Allocate PLTs when loading modules so that jumps and calls whose
1714 targets are too far away for their relative offsets to be encoded
1715 in the instructions themselves can be bounced via veneers in the
1716 module's PLT. This allows modules to be allocated in the generic
1717 vmalloc area after the dedicated module memory area has been
1718 exhausted. The modules will use slightly more memory, but after
1719 rounding up to page size, the actual memory footprint is usually
1722 Say y if you are getting out of memory errors while loading modules
1726 config FORCE_MAX_ZONEORDER
1727 int "Maximum zone order"
1728 default "12" if SOC_AM33XX
1729 default "9" if SA1111 || ARCH_EFM32
1732 The kernel memory allocator divides physically contiguous memory
1733 blocks into "zones", where each zone is a power of two number of
1734 pages. This option selects the largest power of two that the kernel
1735 keeps in the memory allocator. If you need to allocate very large
1736 blocks of physically contiguous memory, then you may need to
1737 increase this value.
1739 This config option is actually maximum order plus one. For example,
1740 a value of 11 means that the largest free memory block is 2^10 pages.
1742 config ALIGNMENT_TRAP
1744 depends on CPU_CP15_MMU
1745 default y if !ARCH_EBSA110
1746 select HAVE_PROC_CPU if PROC_FS
1748 ARM processors cannot fetch/store information which is not
1749 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1750 address divisible by 4. On 32-bit ARM processors, these non-aligned
1751 fetch/store instructions will be emulated in software if you say
1752 here, which has a severe performance impact. This is necessary for
1753 correct operation of some network protocols. With an IP-only
1754 configuration it is safe to say N, otherwise say Y.
1756 config UACCESS_WITH_MEMCPY
1757 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1759 default y if CPU_FEROCEON
1761 Implement faster copy_to_user and clear_user methods for CPU
1762 cores where a 8-word STM instruction give significantly higher
1763 memory write throughput than a sequence of individual 32bit stores.
1765 A possible side effect is a slight increase in scheduling latency
1766 between threads sharing the same address space if they invoke
1767 such copy operations with large buffers.
1769 However, if the CPU data cache is using a write-allocate mode,
1770 this option is unlikely to provide any performance gain.
1774 prompt "Enable seccomp to safely compute untrusted bytecode"
1776 This kernel feature is useful for number crunching applications
1777 that may need to compute untrusted bytecode during their
1778 execution. By using pipes or other transports made available to
1779 the process as file descriptors supporting the read/write
1780 syscalls, it's possible to isolate those applications in
1781 their own address space using seccomp. Once seccomp is
1782 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1783 and the task is only allowed to execute a few safe syscalls
1784 defined by each seccomp mode.
1793 bool "Enable paravirtualization code"
1795 This changes the kernel so it can modify itself when it is run
1796 under a hypervisor, potentially improving performance significantly
1797 over full virtualization.
1799 config PARAVIRT_TIME_ACCOUNTING
1800 bool "Paravirtual steal time accounting"
1804 Select this option to enable fine granularity task steal time
1805 accounting. Time spent executing other tasks in parallel with
1806 the current vCPU is discounted from the vCPU power. To account for
1807 that, there can be a small performance impact.
1809 If in doubt, say N here.
1816 bool "Xen guest support on ARM"
1817 depends on ARM && AEABI && OF
1818 depends on CPU_V7 && !CPU_V6
1819 depends on !GENERIC_ATOMIC64
1821 select ARCH_DMA_ADDR_T_64BIT
1826 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1833 bool "Flattened Device Tree support"
1837 Include support for flattened device tree machine descriptions.
1840 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1843 This is the traditional way of passing data to the kernel at boot
1844 time. If you are solely relying on the flattened device tree (or
1845 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1846 to remove ATAGS support from your kernel binary. If unsure,
1849 config DEPRECATED_PARAM_STRUCT
1850 bool "Provide old way to pass kernel parameters"
1853 This was deprecated in 2001 and announced to live on for 5 years.
1854 Some old boot loaders still use this way.
1856 # Compressed boot loader in ROM. Yes, we really want to ask about
1857 # TEXT and BSS so we preserve their values in the config files.
1858 config ZBOOT_ROM_TEXT
1859 hex "Compressed ROM boot loader base address"
1862 The physical address at which the ROM-able zImage is to be
1863 placed in the target. Platforms which normally make use of
1864 ROM-able zImage formats normally set this to a suitable
1865 value in their defconfig file.
1867 If ZBOOT_ROM is not enabled, this has no effect.
1869 config ZBOOT_ROM_BSS
1870 hex "Compressed ROM boot loader BSS address"
1873 The base address of an area of read/write memory in the target
1874 for the ROM-able zImage which must be available while the
1875 decompressor is running. It must be large enough to hold the
1876 entire decompressed kernel plus an additional 128 KiB.
1877 Platforms which normally make use of ROM-able zImage formats
1878 normally set this to a suitable value in their defconfig file.
1880 If ZBOOT_ROM is not enabled, this has no effect.
1883 bool "Compressed boot loader in ROM/flash"
1884 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1885 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1887 Say Y here if you intend to execute your compressed kernel image
1888 (zImage) directly from ROM or flash. If unsure, say N.
1890 config ARM_APPENDED_DTB
1891 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1894 With this option, the boot code will look for a device tree binary
1895 (DTB) appended to zImage
1896 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1898 This is meant as a backward compatibility convenience for those
1899 systems with a bootloader that can't be upgraded to accommodate
1900 the documented boot protocol using a device tree.
1902 Beware that there is very little in terms of protection against
1903 this option being confused by leftover garbage in memory that might
1904 look like a DTB header after a reboot if no actual DTB is appended
1905 to zImage. Do not leave this option active in a production kernel
1906 if you don't intend to always append a DTB. Proper passing of the
1907 location into r2 of a bootloader provided DTB is always preferable
1910 config ARM_ATAG_DTB_COMPAT
1911 bool "Supplement the appended DTB with traditional ATAG information"
1912 depends on ARM_APPENDED_DTB
1914 Some old bootloaders can't be updated to a DTB capable one, yet
1915 they provide ATAGs with memory configuration, the ramdisk address,
1916 the kernel cmdline string, etc. Such information is dynamically
1917 provided by the bootloader and can't always be stored in a static
1918 DTB. To allow a device tree enabled kernel to be used with such
1919 bootloaders, this option allows zImage to extract the information
1920 from the ATAG list and store it at run time into the appended DTB.
1923 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1924 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1927 bool "Use bootloader kernel arguments if available"
1929 Uses the command-line options passed by the boot loader instead of
1930 the device tree bootargs property. If the boot loader doesn't provide
1931 any, the device tree bootargs property will be used.
1933 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1934 bool "Extend with bootloader kernel arguments"
1936 The command-line arguments provided by the boot loader will be
1937 appended to the the device tree bootargs property.
1942 string "Default kernel command string"
1945 On some architectures (EBSA110 and CATS), there is currently no way
1946 for the boot loader to pass arguments to the kernel. For these
1947 architectures, you should supply some command-line options at build
1948 time by entering them here. As a minimum, you should specify the
1949 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1952 prompt "Kernel command line type" if CMDLINE != ""
1953 default CMDLINE_FROM_BOOTLOADER
1955 config CMDLINE_FROM_BOOTLOADER
1956 bool "Use bootloader kernel arguments if available"
1958 Uses the command-line options passed by the boot loader. If
1959 the boot loader doesn't provide any, the default kernel command
1960 string provided in CMDLINE will be used.
1962 config CMDLINE_EXTEND
1963 bool "Extend bootloader kernel arguments"
1965 The command-line arguments provided by the boot loader will be
1966 appended to the default kernel command string.
1968 config CMDLINE_FORCE
1969 bool "Always use the default kernel command string"
1971 Always use the default kernel command string, even if the boot
1972 loader passes other arguments to the kernel.
1973 This is useful if you cannot or don't want to change the
1974 command-line options your boot loader passes to the kernel.
1978 bool "Kernel Execute-In-Place from ROM"
1979 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1981 Execute-In-Place allows the kernel to run from non-volatile storage
1982 directly addressable by the CPU, such as NOR flash. This saves RAM
1983 space since the text section of the kernel is not loaded from flash
1984 to RAM. Read-write sections, such as the data section and stack,
1985 are still copied to RAM. The XIP kernel is not compressed since
1986 it has to run directly from flash, so it will take more space to
1987 store it. The flash address used to link the kernel object files,
1988 and for storing it, is configuration dependent. Therefore, if you
1989 say Y here, you must know the proper physical address where to
1990 store the kernel image depending on your own flash memory usage.
1992 Also note that the make target becomes "make xipImage" rather than
1993 "make zImage" or "make Image". The final kernel binary to put in
1994 ROM memory will be arch/arm/boot/xipImage.
1998 config XIP_PHYS_ADDR
1999 hex "XIP Kernel Physical Location"
2000 depends on XIP_KERNEL
2001 default "0x00080000"
2003 This is the physical address in your flash memory the kernel will
2004 be linked for and stored to. This address is dependent on your
2008 bool "Kexec system call (EXPERIMENTAL)"
2009 depends on (!SMP || PM_SLEEP_SMP)
2013 kexec is a system call that implements the ability to shutdown your
2014 current kernel, and to start another kernel. It is like a reboot
2015 but it is independent of the system firmware. And like a reboot
2016 you can start any kernel with it, not just Linux.
2018 It is an ongoing process to be certain the hardware in a machine
2019 is properly shutdown, so do not be surprised if this code does not
2020 initially work for you.
2023 bool "Export atags in procfs"
2024 depends on ATAGS && KEXEC
2027 Should the atags used to boot the kernel be exported in an "atags"
2028 file in procfs. Useful with kexec.
2031 bool "Build kdump crash kernel (EXPERIMENTAL)"
2033 Generate crash dump after being started by kexec. This should
2034 be normally only set in special crash dump kernels which are
2035 loaded in the main kernel with kexec-tools into a specially
2036 reserved region and then later executed after a crash by
2037 kdump/kexec. The crash dump kernel must be compiled to a
2038 memory address not used by the main kernel
2040 For more details see Documentation/kdump/kdump.txt
2042 config AUTO_ZRELADDR
2043 bool "Auto calculation of the decompressed kernel image address"
2045 ZRELADDR is the physical address where the decompressed kernel
2046 image will be placed. If AUTO_ZRELADDR is selected, the address
2047 will be determined at run-time by masking the current IP with
2048 0xf8000000. This assumes the zImage being placed in the first 128MB
2049 from start of memory.
2055 bool "UEFI runtime support"
2056 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2058 select EFI_PARAMS_FROM_FDT
2061 select EFI_RUNTIME_WRAPPERS
2063 This option provides support for runtime services provided
2064 by UEFI firmware (such as non-volatile variables, realtime
2065 clock, and platform reset). A UEFI stub is also provided to
2066 allow the kernel to be booted as an EFI application. This
2067 is only useful for kernels that may run on systems that have
2071 bool "Enable support for SMBIOS (DMI) tables"
2075 This enables SMBIOS/DMI feature for systems.
2077 This option is only useful on systems that have UEFI firmware.
2078 However, even with this option, the resultant kernel should
2079 continue to boot on existing non-UEFI platforms.
2081 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2082 i.e., the the practice of identifying the platform via DMI to
2083 decide whether certain workarounds for buggy hardware and/or
2084 firmware need to be enabled. This would require the DMI subsystem
2085 to be enabled much earlier than we do on ARM, which is non-trivial.
2089 menu "CPU Power Management"
2091 source "drivers/cpufreq/Kconfig"
2093 source "drivers/cpuidle/Kconfig"
2097 menu "Floating point emulation"
2099 comment "At least one emulation must be selected"
2102 bool "NWFPE math emulation"
2103 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2105 Say Y to include the NWFPE floating point emulator in the kernel.
2106 This is necessary to run most binaries. Linux does not currently
2107 support floating point hardware so you need to say Y here even if
2108 your machine has an FPA or floating point co-processor podule.
2110 You may say N here if you are going to load the Acorn FPEmulator
2111 early in the bootup.
2114 bool "Support extended precision"
2115 depends on FPE_NWFPE
2117 Say Y to include 80-bit support in the kernel floating-point
2118 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2119 Note that gcc does not generate 80-bit operations by default,
2120 so in most cases this option only enlarges the size of the
2121 floating point emulator without any good reason.
2123 You almost surely want to say N here.
2126 bool "FastFPE math emulation (EXPERIMENTAL)"
2127 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2129 Say Y here to include the FAST floating point emulator in the kernel.
2130 This is an experimental much faster emulator which now also has full
2131 precision for the mantissa. It does not support any exceptions.
2132 It is very simple, and approximately 3-6 times faster than NWFPE.
2134 It should be sufficient for most programs. It may be not suitable
2135 for scientific calculations, but you have to check this for yourself.
2136 If you do not feel you need a faster FP emulation you should better
2140 bool "VFP-format floating point maths"
2141 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2143 Say Y to include VFP support code in the kernel. This is needed
2144 if your hardware includes a VFP unit.
2146 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2147 release notes and additional status information.
2149 Say N if your target does not have VFP hardware.
2157 bool "Advanced SIMD (NEON) Extension support"
2158 depends on VFPv3 && CPU_V7
2160 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2163 config KERNEL_MODE_NEON
2164 bool "Support for NEON in kernel mode"
2165 depends on NEON && AEABI
2167 Say Y to include support for NEON in kernel mode.
2171 menu "Userspace binary formats"
2173 source "fs/Kconfig.binfmt"
2177 menu "Power management options"
2179 source "kernel/power/Kconfig"
2181 config ARCH_SUSPEND_POSSIBLE
2182 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2183 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2186 config ARM_CPU_SUSPEND
2187 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2188 depends on ARCH_SUSPEND_POSSIBLE
2190 config ARCH_HIBERNATION_POSSIBLE
2193 default y if ARCH_SUSPEND_POSSIBLE
2197 source "net/Kconfig"
2199 source "drivers/Kconfig"
2201 source "drivers/firmware/Kconfig"
2205 source "arch/arm/Kconfig.debug"
2207 source "security/Kconfig"
2209 source "crypto/Kconfig"
2211 source "arch/arm/crypto/Kconfig"
2214 source "lib/Kconfig"
2216 source "arch/arm/kvm/Kconfig"