1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CPU_CACHE_ALIASING
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
15 select ARCH_HAS_STRNCPY_FROM_USER
16 select ARCH_HAS_STRNLEN_USER
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_KEEP_MEMBLOCK
21 select ARCH_USE_BUILTIN_BSWAP
22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
23 select ARCH_USE_MEMTEST
24 select ARCH_USE_QUEUED_RWLOCKS
25 select ARCH_USE_QUEUED_SPINLOCKS
26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
28 select ARCH_WANT_IPC_PARSE_VERSION
29 select ARCH_WANT_LD_ORPHAN_WARN
30 select BUILDTIME_TABLE_SORT
31 select CLONE_BACKWARDS
32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
33 select CPU_PM if CPU_IDLE
34 select GENERIC_ATOMIC64 if !64BIT
35 select GENERIC_CMOS_UPDATE
36 select GENERIC_CPU_AUTOPROBE
37 select GENERIC_GETTIMEOFDAY
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_ISA_DMA if EISA
42 select GENERIC_LIB_ASHLDI3
43 select GENERIC_LIB_ASHRDI3
44 select GENERIC_LIB_CMPDI2
45 select GENERIC_LIB_LSHRDI3
46 select GENERIC_LIB_UCMPDI2
47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
48 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_IDLE_POLL_SETUP
50 select GENERIC_TIME_VSYSCALL
51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
53 select HAVE_ARCH_COMPILER_H
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
56 select HAVE_ARCH_MMAP_RND_BITS if MMU
57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
58 select HAVE_ARCH_SECCOMP_FILTER
59 select HAVE_ARCH_TRACEHOOK
60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
61 select HAVE_ASM_MODVERSIONS
62 select HAVE_CONTEXT_TRACKING_USER
64 select HAVE_C_RECORDMCOUNT
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DEBUG_STACKOVERFLOW
67 select HAVE_DMA_CONTIGUOUS
68 select HAVE_DYNAMIC_FTRACE
69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
70 select HAVE_EXIT_THREAD
72 select HAVE_FTRACE_MCOUNT_RECORD
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_FUNCTION_TRACER
75 select HAVE_GCC_PLUGINS
76 select HAVE_GENERIC_VDSO
77 select HAVE_IOREMAP_PROT
78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
79 select HAVE_IRQ_TIME_ACCOUNTING
81 select HAVE_KRETPROBES
82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
83 select HAVE_MOD_ARCH_SPECIFIC
85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
88 select HAVE_PERF_EVENTS
90 select HAVE_PERF_USER_STACK_DUMP
91 select HAVE_REGS_AND_STACK_ACCESS_API
93 select HAVE_SPARSE_SYSCALL_NR
94 select HAVE_STACKPROTECTOR
95 select HAVE_SYSCALL_TRACEPOINTS
96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
97 select IRQ_FORCED_THREADING
99 select LOCK_MM_AND_FIND_VMA
100 select MODULES_USE_ELF_REL if MODULES
101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
102 select PERF_USE_VMALLOC
103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
105 select SYSCTL_EXCEPTION_TRACE
106 select TRACE_IRQFLAGS_SUPPORT
107 select ARCH_HAS_ELFCORE_COMPAT
108 select HAVE_ARCH_KCSAN if 64BIT
110 config MIPS_FIXUP_BIGPHYS_ADDR
116 config MACH_GENERIC_CORE
121 select SYS_SUPPORTS_32BIT_KERNEL
122 select SYS_SUPPORTS_LITTLE_ENDIAN
123 select SYS_SUPPORTS_ZBOOT
124 select DMA_NONCOHERENT
129 select GENERIC_IRQ_CHIP
130 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
132 select CPU_SUPPORTS_CPUFREQ
133 select MIPS_EXTERNAL_TIMER
135 menu "Machine selection"
139 default MIPS_GENERIC_KERNEL
141 config MIPS_GENERIC_KERNEL
142 bool "Generic board-agnostic MIPS kernel"
147 select CLKSRC_MIPS_GIC
149 select CPU_MIPSR2_IRQ_EI
150 select CPU_MIPSR2_IRQ_VI
152 select DMA_NONCOHERENT
155 select MACH_GENERIC_CORE
156 select MIPS_AUTO_PFN_OFFSET
157 select MIPS_CPU_SCACHE
159 select MIPS_L1_CACHE_SHIFT_7
160 select NO_EXCEPT_FILL
161 select PCI_DRIVERS_GENERIC
164 select SYS_HAS_CPU_MIPS32_R1
165 select SYS_HAS_CPU_MIPS32_R2
166 select SYS_HAS_CPU_MIPS32_R5
167 select SYS_HAS_CPU_MIPS32_R6
168 select SYS_HAS_CPU_MIPS64_R1
169 select SYS_HAS_CPU_MIPS64_R2
170 select SYS_HAS_CPU_MIPS64_R5
171 select SYS_HAS_CPU_MIPS64_R6
172 select SYS_SUPPORTS_32BIT_KERNEL
173 select SYS_SUPPORTS_64BIT_KERNEL
174 select SYS_SUPPORTS_BIG_ENDIAN
175 select SYS_SUPPORTS_HIGHMEM
176 select SYS_SUPPORTS_LITTLE_ENDIAN
177 select SYS_SUPPORTS_MICROMIPS
178 select SYS_SUPPORTS_MIPS16
179 select SYS_SUPPORTS_MIPS_CPS
180 select SYS_SUPPORTS_MULTITHREADING
181 select SYS_SUPPORTS_RELOCATABLE
182 select SYS_SUPPORTS_SMARTMIPS
183 select SYS_SUPPORTS_ZBOOT
185 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
186 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
187 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
188 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
189 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
190 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
193 Select this to build a kernel which aims to support multiple boards,
194 generally using a flattened device tree passed from the bootloader
195 using the boot protocol defined in the UHI (Unified Hosting
196 Interface) specification.
199 bool "Alchemy processor based machines"
200 select PHYS_ADDR_T_64BIT
204 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
205 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
206 select SYS_HAS_CPU_MIPS32_R1
207 select SYS_SUPPORTS_32BIT_KERNEL
208 select SYS_SUPPORTS_APM_EMULATION
210 select SYS_SUPPORTS_ZBOOT
214 bool "Atheros AR231x/AR531x SoC support"
217 select DMA_NONCOHERENT
220 select SYS_HAS_CPU_MIPS32_R1
221 select SYS_SUPPORTS_BIG_ENDIAN
222 select SYS_SUPPORTS_32BIT_KERNEL
223 select SYS_HAS_EARLY_PRINTK
225 Support for Atheros AR231x and Atheros AR531x based boards
228 bool "Atheros AR71XX/AR724X/AR913X based boards"
229 select ARCH_HAS_RESET_CONTROLLER
233 select DMA_NONCOHERENT
238 select SYS_HAS_CPU_MIPS32_R2
239 select SYS_HAS_EARLY_PRINTK
240 select SYS_SUPPORTS_32BIT_KERNEL
241 select SYS_SUPPORTS_BIG_ENDIAN
242 select SYS_SUPPORTS_MIPS16
243 select SYS_SUPPORTS_ZBOOT_UART_PROM
245 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
247 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
250 bool "Broadcom Generic BMIPS kernel"
251 select ARCH_HAS_RESET_CONTROLLER
252 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
254 select NO_EXCEPT_FILL
260 select BCM6345_L1_IRQ
261 select BCM7038_L1_IRQ
262 select BCM7120_L2_IRQ
263 select BRCMSTB_L2_IRQ
265 select DMA_NONCOHERENT
266 select SYS_SUPPORTS_32BIT_KERNEL
267 select SYS_SUPPORTS_LITTLE_ENDIAN
268 select SYS_SUPPORTS_BIG_ENDIAN
269 select SYS_SUPPORTS_HIGHMEM
270 select SYS_HAS_CPU_BMIPS32_3300
271 select SYS_HAS_CPU_BMIPS4350
272 select SYS_HAS_CPU_BMIPS4380
273 select SYS_HAS_CPU_BMIPS5000
275 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
276 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
277 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
278 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
279 select HARDIRQS_SW_RESEND
281 select PCI_DRIVERS_GENERIC
284 Build a generic DT-based kernel image that boots on select
285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
287 must be set appropriately for your board.
290 bool "Broadcom BCM47XX based boards"
294 select DMA_NONCOHERENT
297 select SYS_HAS_CPU_MIPS32_R1
298 select NO_EXCEPT_FILL
299 select SYS_SUPPORTS_32BIT_KERNEL
300 select SYS_SUPPORTS_LITTLE_ENDIAN
301 select SYS_SUPPORTS_MIPS16
302 select SYS_SUPPORTS_ZBOOT
303 select SYS_HAS_EARLY_PRINTK
304 select USE_GENERIC_EARLY_PRINTK_8250
306 select LEDS_GPIO_REGISTER
309 select BCM47XX_SSB if !BCM47XX_BCMA
311 Support for BCM47XX based boards
314 bool "Broadcom BCM63XX based boards"
319 select DMA_NONCOHERENT
321 select SYS_SUPPORTS_32BIT_KERNEL
322 select SYS_SUPPORTS_BIG_ENDIAN
323 select SYS_HAS_EARLY_PRINTK
324 select SYS_HAS_CPU_BMIPS32_3300
325 select SYS_HAS_CPU_BMIPS4350
326 select SYS_HAS_CPU_BMIPS4380
329 select MIPS_L1_CACHE_SHIFT_4
330 select HAVE_LEGACY_CLK
332 Support for BCM63XX based boards
339 select DMA_NONCOHERENT
345 select PCI_GT64XXX_PCI0
346 select SYS_HAS_CPU_NEVADA
347 select SYS_HAS_EARLY_PRINTK
348 select SYS_SUPPORTS_32BIT_KERNEL
349 select SYS_SUPPORTS_64BIT_KERNEL
350 select SYS_SUPPORTS_LITTLE_ENDIAN
351 select USE_GENERIC_EARLY_PRINTK_8250
353 config MACH_DECSTATION
357 select CEVT_R4K if CPU_R4X00
359 select CSRC_R4K if CPU_R4X00
360 select CPU_DADDI_WORKAROUNDS if 64BIT
361 select CPU_R4000_WORKAROUNDS if 64BIT
362 select CPU_R4400_WORKAROUNDS if 64BIT
363 select DMA_NONCOHERENT
366 select SYS_HAS_CPU_R3000
367 select SYS_HAS_CPU_R4X00
368 select SYS_SUPPORTS_32BIT_KERNEL
369 select SYS_SUPPORTS_64BIT_KERNEL
370 select SYS_SUPPORTS_LITTLE_ENDIAN
371 select SYS_SUPPORTS_128HZ
372 select SYS_SUPPORTS_256HZ
373 select SYS_SUPPORTS_1024HZ
374 select MIPS_L1_CACHE_SHIFT_4
376 This enables support for DEC's MIPS based workstations. For details
377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
378 DECstation porting pages on <http://decstation.unix-ag.org/>.
380 If you have one of the following DECstation Models you definitely
381 want to choose R4xx0 for the CPU Type:
388 otherwise choose R3000.
391 bool "Jazz family of machines"
394 select ARCH_MIGHT_HAVE_PC_PARPORT
395 select ARCH_MIGHT_HAVE_PC_SERIO
399 select ARCH_MAY_HAVE_PC_FDC
402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
403 select GENERIC_ISA_DMA
404 select HAVE_PCSPKR_PLATFORM
409 select SYS_HAS_CPU_R4X00
410 select SYS_SUPPORTS_32BIT_KERNEL
411 select SYS_SUPPORTS_64BIT_KERNEL
412 select SYS_SUPPORTS_100HZ
413 select SYS_SUPPORTS_LITTLE_ENDIAN
415 This a family of machines based on the MIPS R4030 chipset which was
416 used by several vendors to build RISC/os and Windows NT workstations.
417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
418 Olivetti M700-10 workstations.
420 config MACH_INGENIC_SOC
421 bool "Ingenic SoC based machines"
424 select MACH_GENERIC_CORE
425 select SYS_SUPPORTS_ZBOOT_UART16550
426 select CPU_SUPPORTS_CPUFREQ
427 select MIPS_EXTERNAL_TIMER
430 bool "Lantiq based platforms"
431 select DMA_NONCOHERENT
435 select NO_EXCEPT_FILL
436 select SYS_HAS_CPU_MIPS32_R1
437 select SYS_HAS_CPU_MIPS32_R2
438 select SYS_SUPPORTS_BIG_ENDIAN
439 select SYS_SUPPORTS_32BIT_KERNEL
440 select SYS_SUPPORTS_MIPS16
441 select SYS_SUPPORTS_MULTITHREADING
442 select SYS_SUPPORTS_VPE_LOADER
443 select SYS_HAS_EARLY_PRINTK
447 select HAVE_LEGACY_CLK
450 select PINCTRL_LANTIQ
451 select ARCH_HAS_RESET_CONTROLLER
452 select RESET_CONTROLLER
454 config MACH_LOONGSON32
455 bool "Loongson 32-bit family of machines"
456 select SYS_SUPPORTS_ZBOOT
458 This enables support for the Loongson-1 family of machines.
460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
461 the Institute of Computing Technology (ICT), Chinese Academy of
464 config MACH_LOONGSON2EF
465 bool "Loongson-2E/F family of machines"
466 select SYS_SUPPORTS_ZBOOT
468 This enables the support of early Loongson-2E/F family of machines.
470 config MACH_LOONGSON64
471 bool "Loongson 64-bit family of machines"
472 select ARCH_DMA_DEFAULT_COHERENT
473 select ARCH_SPARSEMEM_ENABLE
474 select ARCH_MIGHT_HAVE_PC_PARPORT
475 select ARCH_MIGHT_HAVE_PC_SERIO
476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
485 select NO_EXCEPT_FILL
486 select NR_CPUS_DEFAULT_64
487 select USE_GENERIC_EARLY_PRINTK_8250
488 select PCI_DRIVERS_GENERIC
489 select SYS_HAS_CPU_LOONGSON64
490 select SYS_HAS_EARLY_PRINTK
491 select SYS_SUPPORTS_SMP
492 select SYS_SUPPORTS_HOTPLUG_CPU
493 select SYS_SUPPORTS_NUMA
494 select SYS_SUPPORTS_64BIT_KERNEL
495 select SYS_SUPPORTS_HIGHMEM
496 select SYS_SUPPORTS_LITTLE_ENDIAN
497 select SYS_SUPPORTS_ZBOOT
498 select SYS_SUPPORTS_RELOCATABLE
503 select PCI_HOST_GENERIC
504 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
506 This enables the support of Loongson-2/3 family of machines.
508 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
509 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
510 and Loongson-2F which will be removed), developed by the Institute
511 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
514 bool "MIPS Malta board"
515 select ARCH_MAY_HAVE_PC_FDC
516 select ARCH_MIGHT_HAVE_PC_PARPORT
517 select ARCH_MIGHT_HAVE_PC_SERIO
522 select CLKSRC_MIPS_GIC
525 select DMA_NONCOHERENT
526 select GENERIC_ISA_DMA
527 select HAVE_PCSPKR_PLATFORM
533 select MIPS_CPU_SCACHE
535 select MIPS_L1_CACHE_SHIFT_6
537 select PCI_GT64XXX_PCI0
540 select SYS_HAS_CPU_MIPS32_R1
541 select SYS_HAS_CPU_MIPS32_R2
542 select SYS_HAS_CPU_MIPS32_R3_5
543 select SYS_HAS_CPU_MIPS32_R5
544 select SYS_HAS_CPU_MIPS32_R6
545 select SYS_HAS_CPU_MIPS64_R1
546 select SYS_HAS_CPU_MIPS64_R2
547 select SYS_HAS_CPU_MIPS64_R6
548 select SYS_HAS_CPU_NEVADA
549 select SYS_HAS_CPU_RM7000
550 select SYS_SUPPORTS_32BIT_KERNEL
551 select SYS_SUPPORTS_64BIT_KERNEL
552 select SYS_SUPPORTS_BIG_ENDIAN
553 select SYS_SUPPORTS_HIGHMEM
554 select SYS_SUPPORTS_LITTLE_ENDIAN
555 select SYS_SUPPORTS_MICROMIPS
556 select SYS_SUPPORTS_MIPS16
557 select SYS_SUPPORTS_MIPS_CPS
558 select SYS_SUPPORTS_MULTITHREADING
559 select SYS_SUPPORTS_RELOCATABLE
560 select SYS_SUPPORTS_SMARTMIPS
561 select SYS_SUPPORTS_VPE_LOADER
562 select SYS_SUPPORTS_ZBOOT
564 select WAR_ICACHE_REFILLS
565 select ZONE_DMA32 if 64BIT
567 This enables support for the MIPS Technologies Malta evaluation
571 bool "Microchip PIC32 Family"
573 This enables support for the Microchip PIC32 family of platforms.
575 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
579 bool "Mobileye EyeQ5 SoC"
580 select MACH_GENERIC_CORE
582 select PHYSICAL_START_BOOL
583 select ARCH_SPARSEMEM_DEFAULT if 64BIT
587 select CLKSRC_MIPS_GIC
589 select CPU_MIPSR2_IRQ_EI
590 select CPU_MIPSR2_IRQ_VI
592 select DMA_NONCOHERENT
595 select MIPS_AUTO_PFN_OFFSET
596 select MIPS_CPU_SCACHE
598 select MIPS_L1_CACHE_SHIFT_7
599 select PCI_DRIVERS_GENERIC
602 select SYS_HAS_CPU_MIPS64_R6
603 select SYS_SUPPORTS_64BIT_KERNEL
604 select SYS_SUPPORTS_HIGHMEM
605 select SYS_SUPPORTS_LITTLE_ENDIAN
606 select SYS_SUPPORTS_MIPS_CPS
607 select SYS_SUPPORTS_RELOCATABLE
608 select SYS_SUPPORTS_ZBOOT
610 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
611 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
612 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
613 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
614 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
615 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
618 Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
622 config MACH_NINTENDO64
623 bool "Nintendo 64 console"
626 select SYS_HAS_CPU_R4300
627 select SYS_SUPPORTS_BIG_ENDIAN
628 select SYS_SUPPORTS_ZBOOT
629 select SYS_SUPPORTS_32BIT_KERNEL
630 select SYS_SUPPORTS_64BIT_KERNEL
631 select DMA_NONCOHERENT
635 bool "Ralink based machines"
640 select DMA_NONCOHERENT
643 select SYS_HAS_CPU_MIPS32_R2
644 select SYS_SUPPORTS_32BIT_KERNEL
645 select SYS_SUPPORTS_LITTLE_ENDIAN
646 select SYS_SUPPORTS_MIPS16
647 select SYS_SUPPORTS_ZBOOT
648 select SYS_HAS_EARLY_PRINTK
649 select ARCH_HAS_RESET_CONTROLLER
650 select RESET_CONTROLLER
652 config MACH_REALTEK_RTL
653 bool "Realtek RTL838x/RTL839x based machines"
655 select MACH_GENERIC_CORE
656 select DMA_NONCOHERENT
660 select SYS_HAS_CPU_MIPS32_R1
661 select SYS_HAS_CPU_MIPS32_R2
662 select SYS_SUPPORTS_BIG_ENDIAN
663 select SYS_SUPPORTS_32BIT_KERNEL
664 select SYS_SUPPORTS_MIPS16
665 select SYS_SUPPORTS_MULTITHREADING
666 select SYS_SUPPORTS_VPE_LOADER
672 bool "SGI IP22 (Indy/Indigo2)"
677 select ARCH_MIGHT_HAVE_PC_SERIO
681 select DEFAULT_SGI_PARTITION
682 select DMA_NONCOHERENT
686 select IP22_CPU_SCACHE
688 select GENERIC_ISA_DMA_SUPPORT_BROKEN
690 select SGI_HAS_INDYDOG
696 select SYS_HAS_CPU_R4X00
697 select SYS_HAS_CPU_R5000
698 select SYS_HAS_EARLY_PRINTK
699 select SYS_SUPPORTS_32BIT_KERNEL
700 select SYS_SUPPORTS_64BIT_KERNEL
701 select SYS_SUPPORTS_BIG_ENDIAN
702 select WAR_R4600_V1_INDEX_ICACHEOP
703 select WAR_R4600_V1_HIT_CACHEOP
704 select WAR_R4600_V2_HIT_CACHEOP
705 select MIPS_L1_CACHE_SHIFT_7
707 This are the SGI Indy, Challenge S and Indigo2, as well as certain
708 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
709 that runs on these, say Y here.
712 bool "SGI IP27 (Origin200/2000)"
713 select ARCH_HAS_PHYS_TO_DMA
714 select ARCH_SPARSEMEM_ENABLE
717 select ARC_CMDLINE_ONLY
719 select DEFAULT_SGI_PARTITION
721 select SYS_HAS_EARLY_PRINTK
724 select IRQ_DOMAIN_HIERARCHY
725 select NR_CPUS_DEFAULT_64
726 select PCI_DRIVERS_GENERIC
727 select PCI_XTALK_BRIDGE
728 select SYS_HAS_CPU_R10000
729 select SYS_SUPPORTS_64BIT_KERNEL
730 select SYS_SUPPORTS_BIG_ENDIAN
731 select SYS_SUPPORTS_NUMA
732 select SYS_SUPPORTS_SMP
733 select WAR_R10000_LLSC
734 select MIPS_L1_CACHE_SHIFT_7
736 select HAVE_ARCH_NODEDATA_EXTENSION
738 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
739 workstations. To compile a Linux kernel that runs on these, say Y
743 bool "SGI IP28 (Indigo2 R10k)"
748 select ARCH_MIGHT_HAVE_PC_SERIO
752 select DEFAULT_SGI_PARTITION
753 select DMA_NONCOHERENT
754 select GENERIC_ISA_DMA_SUPPORT_BROKEN
760 select SGI_HAS_INDYDOG
766 select SYS_HAS_CPU_R10000
767 select SYS_HAS_EARLY_PRINTK
768 select SYS_SUPPORTS_64BIT_KERNEL
769 select SYS_SUPPORTS_BIG_ENDIAN
770 select WAR_R10000_LLSC
771 select MIPS_L1_CACHE_SHIFT_7
773 This is the SGI Indigo2 with R10000 processor. To compile a Linux
774 kernel that runs on these, say Y here.
777 bool "SGI IP30 (Octane/Octane2)"
778 select ARCH_HAS_PHYS_TO_DMA
785 select SYNC_R4K if SMP
789 select IRQ_DOMAIN_HIERARCHY
790 select PCI_DRIVERS_GENERIC
791 select PCI_XTALK_BRIDGE
792 select SYS_HAS_EARLY_PRINTK
793 select SYS_HAS_CPU_R10000
794 select SYS_SUPPORTS_64BIT_KERNEL
795 select SYS_SUPPORTS_BIG_ENDIAN
796 select SYS_SUPPORTS_SMP
797 select WAR_R10000_LLSC
798 select MIPS_L1_CACHE_SHIFT_7
801 These are the SGI Octane and Octane2 graphics workstations. To
802 compile a Linux kernel that runs on these, say Y here.
808 select ARCH_HAS_PHYS_TO_DMA
814 select DMA_NONCOHERENT
817 select R5000_CPU_SCACHE
818 select RM7000_CPU_SCACHE
819 select SYS_HAS_CPU_R5000
820 select SYS_HAS_CPU_R10000 if BROKEN
821 select SYS_HAS_CPU_RM7000
822 select SYS_HAS_CPU_NEVADA
823 select SYS_SUPPORTS_64BIT_KERNEL
824 select SYS_SUPPORTS_BIG_ENDIAN
825 select WAR_ICACHE_REFILLS
827 If you want this kernel to run on SGI O2 workstation, say Y here.
830 bool "Sibyte BCM91125C-CRhone"
832 select SIBYTE_BCM1125
834 select SYS_HAS_CPU_SB1
835 select SYS_SUPPORTS_BIG_ENDIAN
836 select SYS_SUPPORTS_HIGHMEM
837 select SYS_SUPPORTS_LITTLE_ENDIAN
840 bool "Sibyte BCM91125E-Rhone"
844 select SYS_HAS_CPU_SB1
845 select SYS_SUPPORTS_BIG_ENDIAN
846 select SYS_SUPPORTS_LITTLE_ENDIAN
849 bool "Sibyte BCM91250A-SWARM"
851 select HAVE_PATA_PLATFORM
854 select SYS_HAS_CPU_SB1
855 select SYS_SUPPORTS_BIG_ENDIAN
856 select SYS_SUPPORTS_HIGHMEM
857 select SYS_SUPPORTS_LITTLE_ENDIAN
858 select ZONE_DMA32 if 64BIT
859 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
861 config SIBYTE_LITTLESUR
862 bool "Sibyte BCM91250C2-LittleSur"
864 select HAVE_PATA_PLATFORM
867 select SYS_HAS_CPU_SB1
868 select SYS_SUPPORTS_BIG_ENDIAN
869 select SYS_SUPPORTS_HIGHMEM
870 select SYS_SUPPORTS_LITTLE_ENDIAN
871 select ZONE_DMA32 if 64BIT
873 config SIBYTE_SENTOSA
874 bool "Sibyte BCM91250E-Sentosa"
878 select SYS_HAS_CPU_SB1
879 select SYS_SUPPORTS_BIG_ENDIAN
880 select SYS_SUPPORTS_LITTLE_ENDIAN
881 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
884 bool "Sibyte BCM91480B-BigSur"
886 select NR_CPUS_DEFAULT_4
887 select SIBYTE_BCM1x80
889 select SYS_HAS_CPU_SB1
890 select SYS_SUPPORTS_BIG_ENDIAN
891 select SYS_SUPPORTS_HIGHMEM
892 select SYS_SUPPORTS_LITTLE_ENDIAN
893 select ZONE_DMA32 if 64BIT
894 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
897 bool "SNI RM200/300/400"
900 select FW_ARC if CPU_LITTLE_ENDIAN
901 select FW_ARC32 if CPU_LITTLE_ENDIAN
902 select FW_SNIPROM if CPU_BIG_ENDIAN
903 select ARCH_MAY_HAVE_PC_FDC
904 select ARCH_MIGHT_HAVE_PC_PARPORT
905 select ARCH_MIGHT_HAVE_PC_SERIO
909 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
910 select DMA_NONCOHERENT
911 select GENERIC_ISA_DMA
913 select HAVE_PCSPKR_PLATFORM
919 select MIPS_L1_CACHE_SHIFT_6
920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
921 select SYS_HAS_CPU_R4X00
922 select SYS_HAS_CPU_R5000
923 select SYS_HAS_CPU_R10000
924 select R5000_CPU_SCACHE
925 select SYS_HAS_EARLY_PRINTK
926 select SYS_SUPPORTS_32BIT_KERNEL
927 select SYS_SUPPORTS_64BIT_KERNEL
928 select SYS_SUPPORTS_BIG_ENDIAN
929 select SYS_SUPPORTS_HIGHMEM
930 select SYS_SUPPORTS_LITTLE_ENDIAN
931 select WAR_R4600_V2_HIT_CACHEOP
933 The SNI RM200/300/400 are MIPS-based machines manufactured by
934 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
935 Technology and now in turn merged with Fujitsu. Say Y here to
936 support this machine type.
939 bool "Toshiba TX49 series based machines"
940 select WAR_TX49XX_ICACHE_INDEX_INV
942 config MIKROTIK_RB532
943 bool "Mikrotik RB532 boards"
946 select DMA_NONCOHERENT
949 select SYS_HAS_CPU_MIPS32_R1
950 select SYS_SUPPORTS_32BIT_KERNEL
951 select SYS_SUPPORTS_LITTLE_ENDIAN
955 select MIPS_L1_CACHE_SHIFT_4
957 Support the Mikrotik(tm) RouterBoard 532 series,
958 based on the IDT RC32434 SoC.
960 config CAVIUM_OCTEON_SOC
961 bool "Cavium Networks Octeon SoC based boards"
963 select ARCH_HAS_PHYS_TO_DMA
965 select PHYS_ADDR_T_64BIT
966 select SYS_SUPPORTS_64BIT_KERNEL
967 select SYS_SUPPORTS_BIG_ENDIAN
969 select EDAC_ATOMIC_SCRUB
970 select SYS_SUPPORTS_LITTLE_ENDIAN
971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
972 select SYS_HAS_EARLY_PRINTK
973 select SYS_HAS_CPU_CAVIUM_OCTEON
975 select HAVE_PLAT_DELAY
976 select HAVE_PLAT_FW_INIT_CMDLINE
977 select HAVE_PLAT_MEMCPY
981 select ARCH_SPARSEMEM_ENABLE
982 select SYS_SUPPORTS_SMP
983 select NR_CPUS_DEFAULT_64
984 select MIPS_NR_CPU_NR_MAP_1024
987 select MTD_COMPLEX_MAPPINGS
989 select SYS_SUPPORTS_RELOCATABLE
991 This option supports all of the Octeon reference boards from Cavium
992 Networks. It builds a kernel that dynamically determines the Octeon
993 CPU type and supports all known board reference implementations.
994 Some of the supported boards are:
1001 Say Y here for most Octeon reference boards.
1005 config FIT_IMAGE_FDT_EPM5
1006 bool "Include FDT for Mobileye EyeQ5 development platforms"
1007 depends on MACH_EYEQ5
1010 Enable this to include the FDT for the EyeQ5 development platforms
1011 from Mobileye in the FIT kernel image.
1012 This requires u-boot on the platform.
1014 source "arch/mips/alchemy/Kconfig"
1015 source "arch/mips/ath25/Kconfig"
1016 source "arch/mips/ath79/Kconfig"
1017 source "arch/mips/bcm47xx/Kconfig"
1018 source "arch/mips/bcm63xx/Kconfig"
1019 source "arch/mips/bmips/Kconfig"
1020 source "arch/mips/generic/Kconfig"
1021 source "arch/mips/ingenic/Kconfig"
1022 source "arch/mips/jazz/Kconfig"
1023 source "arch/mips/lantiq/Kconfig"
1024 source "arch/mips/pic32/Kconfig"
1025 source "arch/mips/ralink/Kconfig"
1026 source "arch/mips/sgi-ip27/Kconfig"
1027 source "arch/mips/sibyte/Kconfig"
1028 source "arch/mips/txx9/Kconfig"
1029 source "arch/mips/cavium-octeon/Kconfig"
1030 source "arch/mips/loongson2ef/Kconfig"
1031 source "arch/mips/loongson32/Kconfig"
1032 source "arch/mips/loongson64/Kconfig"
1036 config GENERIC_HWEIGHT
1040 config GENERIC_CALIBRATE_DELAY
1044 config SCHED_OMIT_FRAME_POINTER
1049 # Select some configuration options automatically based on user selections.
1054 config ARCH_MAY_HAVE_PC_FDC
1085 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1091 config MIPS_CLOCK_VSYSCALL
1092 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1101 config ARCH_SUPPORTS_UPROBES
1104 config DMA_NONCOHERENT
1107 # MIPS allows mixing "slightly different" Cacheability and Coherency
1108 # Attribute bits. It is believed that the uncached access through
1109 # KSEG1 and the implementation specific "uncached accelerated" used
1110 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1111 # significant advantages.
1113 select ARCH_HAS_SETUP_DMA_OPS
1114 select ARCH_HAS_DMA_WRITE_COMBINE
1115 select ARCH_HAS_DMA_PREP_COHERENT
1116 select ARCH_HAS_SYNC_DMA_FOR_CPU
1117 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1118 select ARCH_HAS_DMA_SET_UNCACHED
1119 select DMA_NONCOHERENT_MMAP
1120 select NEED_DMA_MAP_STATE
1122 config SYS_HAS_EARLY_PRINTK
1125 config SYS_SUPPORTS_HOTPLUG_CPU
1128 config MIPS_BONITO64
1137 config NO_IOPORT_MAP
1141 def_bool CPU_NO_LOAD_STORE_LR
1143 config GENERIC_ISA_DMA
1145 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1148 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1150 select GENERIC_ISA_DMA
1152 config HAVE_PLAT_DELAY
1155 config HAVE_PLAT_FW_INIT_CMDLINE
1158 config HAVE_PLAT_MEMCPY
1164 config SYS_SUPPORTS_RELOCATABLE
1167 Selected if the platform supports relocating the kernel.
1168 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1169 to allow access to command line and entropy sources.
1172 # Endianness selection. Sufficiently obscure so many users don't know what to
1173 # answer,so we try hard to limit the available choices. Also the use of a
1174 # choice statement should be more obvious to the user.
1177 prompt "Endianness selection"
1179 Some MIPS machines can be configured for either little or big endian
1180 byte order. These modes require different kernels and a different
1181 Linux distribution. In general there is one preferred byteorder for a
1182 particular system but some systems are just as commonly used in the
1183 one or the other endianness.
1185 config CPU_BIG_ENDIAN
1187 depends on SYS_SUPPORTS_BIG_ENDIAN
1189 config CPU_LITTLE_ENDIAN
1190 bool "Little endian"
1191 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1198 config SYS_SUPPORTS_APM_EMULATION
1201 config SYS_SUPPORTS_BIG_ENDIAN
1204 config SYS_SUPPORTS_LITTLE_ENDIAN
1207 config MIPS_HUGE_TLB_SUPPORT
1208 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1216 config PCI_GT64XXX_PCI0
1219 config PCI_XTALK_BRIDGE
1222 config NO_EXCEPT_FILL
1228 config SWAP_IO_SPACE
1231 config SGI_HAS_INDYDOG
1243 config SGI_HAS_ZILOG
1246 config SGI_HAS_I8042
1249 config DEFAULT_SGI_PARTITION
1261 config MIPS_L1_CACHE_SHIFT_4
1264 config MIPS_L1_CACHE_SHIFT_5
1267 config MIPS_L1_CACHE_SHIFT_6
1270 config MIPS_L1_CACHE_SHIFT_7
1273 config MIPS_L1_CACHE_SHIFT
1275 default "7" if MIPS_L1_CACHE_SHIFT_7
1276 default "6" if MIPS_L1_CACHE_SHIFT_6
1277 default "5" if MIPS_L1_CACHE_SHIFT_5
1278 default "4" if MIPS_L1_CACHE_SHIFT_4
1281 config ARC_CMDLINE_ONLY
1285 bool "ARC console support"
1286 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1300 menu "CPU selection"
1306 config CPU_LOONGSON64
1307 bool "Loongson 64-bit CPU"
1308 depends on SYS_HAS_CPU_LOONGSON64
1309 select ARCH_HAS_PHYS_TO_DMA
1311 select CPU_HAS_PREFETCH
1312 select CPU_SUPPORTS_64BIT_KERNEL
1313 select CPU_SUPPORTS_HIGHMEM
1314 select CPU_SUPPORTS_HUGEPAGES
1315 select CPU_SUPPORTS_MSA
1316 select CPU_SUPPORTS_VZ
1317 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1318 select CPU_MIPSR2_IRQ_VI
1319 select DMA_NONCOHERENT
1320 select WEAK_ORDERING
1321 select WEAK_REORDERING_BEYOND_LLSC
1322 select MIPS_ASID_BITS_VARIABLE
1323 select MIPS_PGD_C0_CONTEXT
1324 select MIPS_L1_CACHE_SHIFT_6
1325 select MIPS_FP_SUPPORT
1329 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1330 cores implements the MIPS64R2 instruction set with many extensions,
1331 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1332 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1333 Loongson-2E/2F is not covered here and will be removed in future.
1335 config CPU_LOONGSON2E
1337 depends on SYS_HAS_CPU_LOONGSON2E
1338 select CPU_LOONGSON2EF
1340 The Loongson 2E processor implements the MIPS III instruction set
1341 with many extensions.
1343 It has an internal FPGA northbridge, which is compatible to
1346 config CPU_LOONGSON2F
1348 depends on SYS_HAS_CPU_LOONGSON2F
1349 select CPU_LOONGSON2EF
1351 The Loongson 2F processor implements the MIPS III instruction set
1352 with many extensions.
1354 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1355 have a similar programming interface with FPGA northbridge used in
1358 config CPU_LOONGSON1B
1360 depends on SYS_HAS_CPU_LOONGSON1B
1361 select CPU_LOONGSON32
1362 select LEDS_GPIO_REGISTER
1364 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1365 Release 1 instruction set and part of the MIPS32 Release 2
1368 config CPU_LOONGSON1C
1370 depends on SYS_HAS_CPU_LOONGSON1C
1371 select CPU_LOONGSON32
1372 select LEDS_GPIO_REGISTER
1374 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1375 Release 1 instruction set and part of the MIPS32 Release 2
1378 config CPU_MIPS32_R1
1379 bool "MIPS32 Release 1"
1380 depends on SYS_HAS_CPU_MIPS32_R1
1381 select CPU_HAS_PREFETCH
1382 select CPU_SUPPORTS_32BIT_KERNEL
1383 select CPU_SUPPORTS_HIGHMEM
1385 Choose this option to build a kernel for release 1 or later of the
1386 MIPS32 architecture. Most modern embedded systems with a 32-bit
1387 MIPS processor are based on a MIPS32 processor. If you know the
1388 specific type of processor in your system, choose those that one
1389 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1390 Release 2 of the MIPS32 architecture is available since several
1391 years so chances are you even have a MIPS32 Release 2 processor
1392 in which case you should choose CPU_MIPS32_R2 instead for better
1395 config CPU_MIPS32_R2
1396 bool "MIPS32 Release 2"
1397 depends on SYS_HAS_CPU_MIPS32_R2
1398 select CPU_HAS_PREFETCH
1399 select CPU_SUPPORTS_32BIT_KERNEL
1400 select CPU_SUPPORTS_HIGHMEM
1401 select CPU_SUPPORTS_MSA
1403 Choose this option to build a kernel for release 2 or later of the
1404 MIPS32 architecture. Most modern embedded systems with a 32-bit
1405 MIPS processor are based on a MIPS32 processor. If you know the
1406 specific type of processor in your system, choose those that one
1407 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1409 config CPU_MIPS32_R5
1410 bool "MIPS32 Release 5"
1411 depends on SYS_HAS_CPU_MIPS32_R5
1412 select CPU_HAS_PREFETCH
1413 select CPU_SUPPORTS_32BIT_KERNEL
1414 select CPU_SUPPORTS_HIGHMEM
1415 select CPU_SUPPORTS_MSA
1416 select CPU_SUPPORTS_VZ
1417 select MIPS_O32_FP64_SUPPORT
1419 Choose this option to build a kernel for release 5 or later of the
1420 MIPS32 architecture. New MIPS processors, starting with the Warrior
1421 family, are based on a MIPS32r5 processor. If you own an older
1422 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1424 config CPU_MIPS32_R6
1425 bool "MIPS32 Release 6"
1426 depends on SYS_HAS_CPU_MIPS32_R6
1427 select CPU_HAS_PREFETCH
1428 select CPU_NO_LOAD_STORE_LR
1429 select CPU_SUPPORTS_32BIT_KERNEL
1430 select CPU_SUPPORTS_HIGHMEM
1431 select CPU_SUPPORTS_MSA
1432 select CPU_SUPPORTS_VZ
1433 select MIPS_O32_FP64_SUPPORT
1435 Choose this option to build a kernel for release 6 or later of the
1436 MIPS32 architecture. New MIPS processors, starting with the Warrior
1437 family, are based on a MIPS32r6 processor. If you own an older
1438 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1440 config CPU_MIPS64_R1
1441 bool "MIPS64 Release 1"
1442 depends on SYS_HAS_CPU_MIPS64_R1
1443 select CPU_HAS_PREFETCH
1444 select CPU_SUPPORTS_32BIT_KERNEL
1445 select CPU_SUPPORTS_64BIT_KERNEL
1446 select CPU_SUPPORTS_HIGHMEM
1447 select CPU_SUPPORTS_HUGEPAGES
1449 Choose this option to build a kernel for release 1 or later of the
1450 MIPS64 architecture. Many modern embedded systems with a 64-bit
1451 MIPS processor are based on a MIPS64 processor. If you know the
1452 specific type of processor in your system, choose those that one
1453 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1454 Release 2 of the MIPS64 architecture is available since several
1455 years so chances are you even have a MIPS64 Release 2 processor
1456 in which case you should choose CPU_MIPS64_R2 instead for better
1459 config CPU_MIPS64_R2
1460 bool "MIPS64 Release 2"
1461 depends on SYS_HAS_CPU_MIPS64_R2
1462 select CPU_HAS_PREFETCH
1463 select CPU_SUPPORTS_32BIT_KERNEL
1464 select CPU_SUPPORTS_64BIT_KERNEL
1465 select CPU_SUPPORTS_HIGHMEM
1466 select CPU_SUPPORTS_HUGEPAGES
1467 select CPU_SUPPORTS_MSA
1469 Choose this option to build a kernel for release 2 or later of the
1470 MIPS64 architecture. Many modern embedded systems with a 64-bit
1471 MIPS processor are based on a MIPS64 processor. If you know the
1472 specific type of processor in your system, choose those that one
1473 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1475 config CPU_MIPS64_R5
1476 bool "MIPS64 Release 5"
1477 depends on SYS_HAS_CPU_MIPS64_R5
1478 select CPU_HAS_PREFETCH
1479 select CPU_SUPPORTS_32BIT_KERNEL
1480 select CPU_SUPPORTS_64BIT_KERNEL
1481 select CPU_SUPPORTS_HIGHMEM
1482 select CPU_SUPPORTS_HUGEPAGES
1483 select CPU_SUPPORTS_MSA
1484 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1485 select CPU_SUPPORTS_VZ
1487 Choose this option to build a kernel for release 5 or later of the
1488 MIPS64 architecture. This is a intermediate MIPS architecture
1489 release partly implementing release 6 features. Though there is no
1490 any hardware known to be based on this release.
1492 config CPU_MIPS64_R6
1493 bool "MIPS64 Release 6"
1494 depends on SYS_HAS_CPU_MIPS64_R6
1495 select CPU_HAS_PREFETCH
1496 select CPU_NO_LOAD_STORE_LR
1497 select CPU_SUPPORTS_32BIT_KERNEL
1498 select CPU_SUPPORTS_64BIT_KERNEL
1499 select CPU_SUPPORTS_HIGHMEM
1500 select CPU_SUPPORTS_HUGEPAGES
1501 select CPU_SUPPORTS_MSA
1502 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1503 select CPU_SUPPORTS_VZ
1505 Choose this option to build a kernel for release 6 or later of the
1506 MIPS64 architecture. New MIPS processors, starting with the Warrior
1507 family, are based on a MIPS64r6 processor. If you own an older
1508 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1511 bool "MIPS Warrior P5600"
1512 depends on SYS_HAS_CPU_P5600
1513 select CPU_HAS_PREFETCH
1514 select CPU_SUPPORTS_32BIT_KERNEL
1515 select CPU_SUPPORTS_HIGHMEM
1516 select CPU_SUPPORTS_MSA
1517 select CPU_SUPPORTS_CPUFREQ
1518 select CPU_SUPPORTS_VZ
1519 select CPU_MIPSR2_IRQ_VI
1520 select CPU_MIPSR2_IRQ_EI
1521 select MIPS_O32_FP64_SUPPORT
1523 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1524 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1525 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1526 level features like up to six P5600 calculation cores, CM2 with L2
1527 cache, IOCU/IOMMU (though might be unused depending on the system-
1528 specific IP core configuration), GIC, CPC, virtualisation module,
1533 depends on SYS_HAS_CPU_R3000
1536 select CPU_SUPPORTS_32BIT_KERNEL
1537 select CPU_SUPPORTS_HIGHMEM
1539 Please make sure to pick the right CPU type. Linux/MIPS is not
1540 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1541 *not* work on R4000 machines and vice versa. However, since most
1542 of the supported machines have an R4000 (or similar) CPU, R4x00
1543 might be a safe bet. If the resulting kernel does not work,
1544 try to recompile with R3000.
1548 depends on SYS_HAS_CPU_R4300
1549 select CPU_SUPPORTS_32BIT_KERNEL
1550 select CPU_SUPPORTS_64BIT_KERNEL
1552 MIPS Technologies R4300-series processors.
1556 depends on SYS_HAS_CPU_R4X00
1557 select CPU_SUPPORTS_32BIT_KERNEL
1558 select CPU_SUPPORTS_64BIT_KERNEL
1559 select CPU_SUPPORTS_HUGEPAGES
1561 MIPS Technologies R4000-series processors other than 4300, including
1562 the R4000, R4400, R4600, and 4700.
1566 depends on SYS_HAS_CPU_TX49XX
1567 select CPU_HAS_PREFETCH
1568 select CPU_SUPPORTS_32BIT_KERNEL
1569 select CPU_SUPPORTS_64BIT_KERNEL
1570 select CPU_SUPPORTS_HUGEPAGES
1574 depends on SYS_HAS_CPU_R5000
1575 select CPU_SUPPORTS_32BIT_KERNEL
1576 select CPU_SUPPORTS_64BIT_KERNEL
1577 select CPU_SUPPORTS_HUGEPAGES
1579 MIPS Technologies R5000-series processors other than the Nevada.
1583 depends on SYS_HAS_CPU_R5500
1584 select CPU_SUPPORTS_32BIT_KERNEL
1585 select CPU_SUPPORTS_64BIT_KERNEL
1586 select CPU_SUPPORTS_HUGEPAGES
1588 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1593 depends on SYS_HAS_CPU_NEVADA
1594 select CPU_SUPPORTS_32BIT_KERNEL
1595 select CPU_SUPPORTS_64BIT_KERNEL
1596 select CPU_SUPPORTS_HUGEPAGES
1598 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1602 depends on SYS_HAS_CPU_R10000
1603 select CPU_HAS_PREFETCH
1604 select CPU_SUPPORTS_32BIT_KERNEL
1605 select CPU_SUPPORTS_64BIT_KERNEL
1606 select CPU_SUPPORTS_HIGHMEM
1607 select CPU_SUPPORTS_HUGEPAGES
1609 MIPS Technologies R10000-series processors.
1613 depends on SYS_HAS_CPU_RM7000
1614 select CPU_HAS_PREFETCH
1615 select CPU_SUPPORTS_32BIT_KERNEL
1616 select CPU_SUPPORTS_64BIT_KERNEL
1617 select CPU_SUPPORTS_HIGHMEM
1618 select CPU_SUPPORTS_HUGEPAGES
1622 depends on SYS_HAS_CPU_SB1
1623 select CPU_SUPPORTS_32BIT_KERNEL
1624 select CPU_SUPPORTS_64BIT_KERNEL
1625 select CPU_SUPPORTS_HIGHMEM
1626 select CPU_SUPPORTS_HUGEPAGES
1627 select WEAK_ORDERING
1629 config CPU_CAVIUM_OCTEON
1630 bool "Cavium Octeon processor"
1631 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1632 select CPU_HAS_PREFETCH
1633 select CPU_SUPPORTS_64BIT_KERNEL
1634 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
1635 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
1636 select WEAK_ORDERING
1637 select CPU_SUPPORTS_HIGHMEM
1638 select CPU_SUPPORTS_HUGEPAGES
1639 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1640 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1641 select MIPS_L1_CACHE_SHIFT_7
1642 select CPU_SUPPORTS_VZ
1644 The Cavium Octeon processor is a highly integrated chip containing
1645 many ethernet hardware widgets for networking tasks. The processor
1646 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1647 Full details can be found at http://www.caviumnetworks.com.
1650 bool "Broadcom BMIPS"
1651 depends on SYS_HAS_CPU_BMIPS
1653 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1654 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1655 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1656 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1657 select CPU_SUPPORTS_32BIT_KERNEL
1658 select DMA_NONCOHERENT
1660 select SWAP_IO_SPACE
1661 select WEAK_ORDERING
1662 select CPU_SUPPORTS_HIGHMEM
1663 select CPU_HAS_PREFETCH
1664 select CPU_SUPPORTS_CPUFREQ
1665 select MIPS_EXTERNAL_TIMER
1666 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1668 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1672 config LOONGSON3_ENHANCEMENT
1673 bool "New Loongson-3 CPU Enhancements"
1675 depends on CPU_LOONGSON64
1677 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1678 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1679 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1680 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1681 Fast TLB refill support, etc.
1683 This option enable those enhancements which are not probed at run
1684 time. If you want a generic kernel to run on all Loongson 3 machines,
1685 please say 'N' here. If you want a high-performance kernel to run on
1686 new Loongson-3 machines only, please say 'Y' here.
1688 config CPU_LOONGSON3_WORKAROUNDS
1689 bool "Loongson-3 LLSC Workarounds"
1691 depends on CPU_LOONGSON64
1693 Loongson-3 processors have the llsc issues which require workarounds.
1694 Without workarounds the system may hang unexpectedly.
1696 Say Y, unless you know what you are doing.
1698 config CPU_LOONGSON3_CPUCFG_EMULATION
1699 bool "Emulate the CPUCFG instruction on older Loongson cores"
1701 depends on CPU_LOONGSON64
1703 Loongson-3A R4 and newer have the CPUCFG instruction available for
1704 userland to query CPU capabilities, much like CPUID on x86. This
1705 option provides emulation of the instruction on older Loongson
1706 cores, back to Loongson-3A1000.
1708 If unsure, please say Y.
1710 config CPU_MIPS32_3_5_FEATURES
1711 bool "MIPS32 Release 3.5 Features"
1712 depends on SYS_HAS_CPU_MIPS32_R3_5
1713 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1716 Choose this option to build a kernel for release 2 or later of the
1717 MIPS32 architecture including features from the 3.5 release such as
1718 support for Enhanced Virtual Addressing (EVA).
1720 config CPU_MIPS32_3_5_EVA
1721 bool "Enhanced Virtual Addressing (EVA)"
1722 depends on CPU_MIPS32_3_5_FEATURES
1726 Choose this option if you want to enable the Enhanced Virtual
1727 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1728 One of its primary benefits is an increase in the maximum size
1729 of lowmem (up to 3GB). If unsure, say 'N' here.
1731 config CPU_MIPS32_R5_FEATURES
1732 bool "MIPS32 Release 5 Features"
1733 depends on SYS_HAS_CPU_MIPS32_R5
1734 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1736 Choose this option to build a kernel for release 2 or later of the
1737 MIPS32 architecture including features from release 5 such as
1738 support for Extended Physical Addressing (XPA).
1740 config CPU_MIPS32_R5_XPA
1741 bool "Extended Physical Addressing (XPA)"
1742 depends on CPU_MIPS32_R5_FEATURES
1744 depends on !PAGE_SIZE_4KB
1745 depends on SYS_SUPPORTS_HIGHMEM
1748 select PHYS_ADDR_T_64BIT
1751 Choose this option if you want to enable the Extended Physical
1752 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1753 benefit is to increase physical addressing equal to or greater
1754 than 40 bits. Note that this has the side effect of turning on
1755 64-bit addressing which in turn makes the PTEs 64-bit in size.
1756 If unsure, say 'N' here.
1759 config CPU_NOP_WORKAROUNDS
1762 config CPU_JUMP_WORKAROUNDS
1765 config CPU_LOONGSON2F_WORKAROUNDS
1766 bool "Loongson 2F Workarounds"
1768 select CPU_NOP_WORKAROUNDS
1769 select CPU_JUMP_WORKAROUNDS
1771 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1772 require workarounds. Without workarounds the system may hang
1773 unexpectedly. For more information please refer to the gas
1774 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1776 Loongson 2F03 and later have fixed these issues and no workarounds
1777 are needed. The workarounds have no significant side effect on them
1778 but may decrease the performance of the system so this option should
1779 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1782 If unsure, please say Y.
1783 endif # CPU_LOONGSON2F
1785 config SYS_SUPPORTS_ZBOOT
1787 select HAVE_KERNEL_GZIP
1788 select HAVE_KERNEL_BZIP2
1789 select HAVE_KERNEL_LZ4
1790 select HAVE_KERNEL_LZMA
1791 select HAVE_KERNEL_LZO
1792 select HAVE_KERNEL_XZ
1793 select HAVE_KERNEL_ZSTD
1795 config SYS_SUPPORTS_ZBOOT_UART16550
1797 select SYS_SUPPORTS_ZBOOT
1799 config SYS_SUPPORTS_ZBOOT_UART_PROM
1801 select SYS_SUPPORTS_ZBOOT
1803 config CPU_LOONGSON2EF
1805 select CPU_SUPPORTS_32BIT_KERNEL
1806 select CPU_SUPPORTS_64BIT_KERNEL
1807 select CPU_SUPPORTS_HIGHMEM
1808 select CPU_SUPPORTS_HUGEPAGES
1810 config CPU_LOONGSON32
1814 select CPU_HAS_PREFETCH
1815 select CPU_SUPPORTS_32BIT_KERNEL
1816 select CPU_SUPPORTS_HIGHMEM
1817 select CPU_SUPPORTS_CPUFREQ
1819 config CPU_BMIPS32_3300
1820 select SMP_UP if SMP
1823 config CPU_BMIPS4350
1825 select SYS_SUPPORTS_SMP
1826 select SYS_SUPPORTS_HOTPLUG_CPU
1828 config CPU_BMIPS4380
1830 select MIPS_L1_CACHE_SHIFT_6
1831 select SYS_SUPPORTS_SMP
1832 select SYS_SUPPORTS_HOTPLUG_CPU
1835 config CPU_BMIPS5000
1837 select MIPS_CPU_SCACHE
1838 select MIPS_L1_CACHE_SHIFT_7
1839 select SYS_SUPPORTS_SMP
1840 select SYS_SUPPORTS_HOTPLUG_CPU
1843 config SYS_HAS_CPU_LOONGSON64
1845 select CPU_SUPPORTS_CPUFREQ
1848 config SYS_HAS_CPU_LOONGSON2E
1851 config SYS_HAS_CPU_LOONGSON2F
1853 select CPU_SUPPORTS_CPUFREQ
1854 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1856 config SYS_HAS_CPU_LOONGSON1B
1859 config SYS_HAS_CPU_LOONGSON1C
1862 config SYS_HAS_CPU_MIPS32_R1
1865 config SYS_HAS_CPU_MIPS32_R2
1868 config SYS_HAS_CPU_MIPS32_R3_5
1871 config SYS_HAS_CPU_MIPS32_R5
1874 config SYS_HAS_CPU_MIPS32_R6
1877 config SYS_HAS_CPU_MIPS64_R1
1880 config SYS_HAS_CPU_MIPS64_R2
1883 config SYS_HAS_CPU_MIPS64_R5
1886 config SYS_HAS_CPU_MIPS64_R6
1889 config SYS_HAS_CPU_P5600
1892 config SYS_HAS_CPU_R3000
1895 config SYS_HAS_CPU_R4300
1898 config SYS_HAS_CPU_R4X00
1901 config SYS_HAS_CPU_TX49XX
1904 config SYS_HAS_CPU_R5000
1907 config SYS_HAS_CPU_R5500
1910 config SYS_HAS_CPU_NEVADA
1913 config SYS_HAS_CPU_R10000
1916 config SYS_HAS_CPU_RM7000
1919 config SYS_HAS_CPU_SB1
1922 config SYS_HAS_CPU_CAVIUM_OCTEON
1925 config SYS_HAS_CPU_BMIPS
1928 config SYS_HAS_CPU_BMIPS32_3300
1930 select SYS_HAS_CPU_BMIPS
1932 config SYS_HAS_CPU_BMIPS4350
1934 select SYS_HAS_CPU_BMIPS
1936 config SYS_HAS_CPU_BMIPS4380
1938 select SYS_HAS_CPU_BMIPS
1940 config SYS_HAS_CPU_BMIPS5000
1942 select SYS_HAS_CPU_BMIPS
1945 # CPU may reorder R->R, R->W, W->R, W->W
1946 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1948 config WEAK_ORDERING
1952 # CPU may reorder reads and writes beyond LL/SC
1953 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1955 config WEAK_REORDERING_BEYOND_LLSC
1960 # These two indicate any level of the MIPS32 and MIPS64 architecture
1964 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1965 CPU_MIPS32_R6 || CPU_P5600
1969 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1970 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1973 # These indicate the revision of the architecture
1977 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1981 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1983 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1988 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1990 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1995 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1997 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1998 select HAVE_ARCH_BITREVERSE
1999 select MIPS_ASID_BITS_VARIABLE
2000 select MIPS_CRC_SUPPORT
2003 config TARGET_ISA_REV
2005 default 1 if CPU_MIPSR1
2006 default 2 if CPU_MIPSR2
2007 default 5 if CPU_MIPSR5
2008 default 6 if CPU_MIPSR6
2011 Reflects the ISA revision being targeted by the kernel build. This
2012 is effectively the Kconfig equivalent of MIPS_ISA_REV.
2020 config SYS_SUPPORTS_32BIT_KERNEL
2022 config SYS_SUPPORTS_64BIT_KERNEL
2024 config CPU_SUPPORTS_32BIT_KERNEL
2026 config CPU_SUPPORTS_64BIT_KERNEL
2028 config CPU_SUPPORTS_CPUFREQ
2030 config CPU_SUPPORTS_ADDRWINCFG
2032 config CPU_SUPPORTS_HUGEPAGES
2034 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
2035 config CPU_SUPPORTS_VZ
2037 config MIPS_PGD_C0_CONTEXT
2040 default y if (CPU_MIPSR2 || CPU_MIPSR6)
2043 # Set to y for ptrace access to watch registers.
2045 config HARDWARE_WATCHPOINTS
2047 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
2052 prompt "Kernel code model"
2054 You should only select this option if you have a workload that
2055 actually benefits from 64-bit processing or if your machine has
2056 large memory. You will only be presented a single option in this
2057 menu if your system does not support both 32-bit and 64-bit kernels.
2060 bool "32-bit kernel"
2061 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
2064 Select this option if you want to build a 32-bit kernel.
2067 bool "64-bit kernel"
2068 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2070 Select this option if you want to build a 64-bit kernel.
2074 config MIPS_VA_BITS_48
2075 bool "48 bits virtual memory"
2078 Support a maximum at least 48 bits of application virtual
2079 memory. Default is 40 bits or less, depending on the CPU.
2080 For page sizes 16k and above, this option results in a small
2081 memory overhead for page tables. For 4k page size, a fourth
2082 level of page tables is added which imposes both a memory
2083 overhead as well as slower TLB fault handling.
2087 config ZBOOT_LOAD_ADDRESS
2088 hex "Compressed kernel load address"
2089 default 0xffffffff80400000 if BCM47XX
2091 depends on SYS_SUPPORTS_ZBOOT
2093 The address to load compressed kernel, aka vmlinuz.
2095 This is only used if non-zero.
2097 config ARCH_FORCE_MAX_ORDER
2098 int "Maximum zone order"
2099 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2100 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2101 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2104 The kernel memory allocator divides physically contiguous memory
2105 blocks into "zones", where each zone is a power of two number of
2106 pages. This option selects the largest power of two that the kernel
2107 keeps in the memory allocator. If you need to allocate very large
2108 blocks of physically contiguous memory, then you may need to
2109 increase this value.
2111 The page size is not necessarily 4KB. Keep this in mind
2112 when choosing a value for this option.
2117 config IP22_CPU_SCACHE
2122 # Support for a MIPS32 / MIPS64 style S-caches
2124 config MIPS_CPU_SCACHE
2128 config R5000_CPU_SCACHE
2132 config RM7000_CPU_SCACHE
2136 config SIBYTE_DMA_PAGEOPS
2137 bool "Use DMA to clear/copy pages"
2140 Instead of using the CPU to zero and copy pages, use a Data Mover
2141 channel. These DMA channels are otherwise unused by the standard
2142 SiByte Linux port. Seems to give a small performance benefit.
2144 config CPU_HAS_PREFETCH
2147 config CPU_GENERIC_DUMP_TLB
2149 default y if !CPU_R3000
2151 config MIPS_FP_SUPPORT
2152 bool "Floating Point support" if EXPERT
2155 Select y to include support for floating point in the kernel
2156 including initialization of FPU hardware, FP context save & restore
2157 and emulation of an FPU where necessary. Without this support any
2158 userland program attempting to use floating point instructions will
2161 If you know that your userland will not attempt to use floating point
2162 instructions then you can say n here to shrink the kernel a little.
2166 config CPU_R2300_FPU
2168 depends on MIPS_FP_SUPPORT
2169 default y if CPU_R3000
2176 depends on MIPS_FP_SUPPORT
2177 default y if !CPU_R2300_FPU
2179 config CPU_R4K_CACHE_TLB
2181 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2184 bool "MIPS MT SMP support (1 TC on each available VPE)"
2186 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
2187 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
2188 select CPU_MIPSR2_IRQ_VI
2189 select CPU_MIPSR2_IRQ_EI
2194 select SYS_SUPPORTS_SMP
2195 select SYS_SUPPORTS_SCHED_SMT
2196 select MIPS_PERF_SHARED_TC_COUNTERS
2198 This is a kernel model which is known as SMVP. This is supported
2199 on cores with the MT ASE and uses the available VPEs to implement
2200 virtual processors which supports SMP. This is equivalent to the
2201 Intel Hyperthreading feature. For further information go to
2202 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2208 bool "SMT (multithreading) scheduler support"
2209 depends on SYS_SUPPORTS_SCHED_SMT
2212 SMT scheduler support improves the CPU scheduler's decision making
2213 when dealing with MIPS MT enabled cores at a cost of slightly
2214 increased overhead in some places. If unsure say N here.
2216 config SYS_SUPPORTS_SCHED_SMT
2219 config SYS_SUPPORTS_MULTITHREADING
2222 config MIPS_MT_FPAFF
2223 bool "Dynamic FPU affinity for FP-intensive threads"
2225 depends on MIPS_MT_SMP
2227 config MIPSR2_TO_R6_EMULATOR
2228 bool "MIPS R2-to-R6 emulator"
2229 depends on CPU_MIPSR6
2230 depends on MIPS_FP_SUPPORT
2233 Choose this option if you want to run non-R6 MIPS userland code.
2234 Even if you say 'Y' here, the emulator will still be disabled by
2235 default. You can enable it using the 'mipsr2emu' kernel option.
2236 The only reason this is a build-time option is to save ~14K from the
2239 config SYS_SUPPORTS_VPE_LOADER
2241 depends on SYS_SUPPORTS_MULTITHREADING
2243 Indicates that the platform supports the VPE loader, and provides
2246 config MIPS_VPE_LOADER
2247 bool "VPE loader support."
2248 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2249 select CPU_MIPSR2_IRQ_VI
2250 select CPU_MIPSR2_IRQ_EI
2253 Includes a loader for loading an elf relocatable object
2254 onto another VPE and running it.
2256 config MIPS_VPE_LOADER_MT
2259 depends on MIPS_VPE_LOADER
2261 config MIPS_VPE_LOADER_TOM
2262 bool "Load VPE program into memory hidden from linux"
2263 depends on MIPS_VPE_LOADER
2266 The loader can use memory that is present but has been hidden from
2267 Linux using the kernel command line option "mem=xxMB". It's up to
2268 you to ensure the amount you put in the option and the space your
2269 program requires is less or equal to the amount physically present.
2271 config MIPS_VPE_APSP_API
2272 bool "Enable support for AP/SP API (RTLX)"
2273 depends on MIPS_VPE_LOADER
2275 config MIPS_VPE_APSP_API_MT
2278 depends on MIPS_VPE_APSP_API
2281 bool "MIPS Coherent Processing System support"
2282 depends on SYS_SUPPORTS_MIPS_CPS
2284 select MIPS_CPS_PM if HOTPLUG_CPU
2286 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2287 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2288 select SYS_SUPPORTS_HOTPLUG_CPU
2289 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2290 select SYS_SUPPORTS_SMP
2291 select WEAK_ORDERING
2292 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2294 Select this if you wish to run an SMP kernel across multiple cores
2295 within a MIPS Coherent Processing System. When this option is
2296 enabled the kernel will probe for other cores and boot them with
2297 no external assistance. It is safe to enable this when hardware
2298 support is unavailable.
2311 config SB1_PASS_2_WORKAROUNDS
2313 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2316 config SB1_PASS_2_1_WORKAROUNDS
2318 depends on CPU_SB1 && CPU_SB1_PASS_2
2322 prompt "SmartMIPS or microMIPS ASE support"
2324 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2327 Select this if you want neither microMIPS nor SmartMIPS support
2329 config CPU_HAS_SMARTMIPS
2330 depends on SYS_SUPPORTS_SMARTMIPS
2333 SmartMIPS is a extension of the MIPS32 architecture aimed at
2334 increased security at both hardware and software level for
2335 smartcards. Enabling this option will allow proper use of the
2336 SmartMIPS instructions by Linux applications. However a kernel with
2337 this option will not work on a MIPS core without SmartMIPS core. If
2338 you don't know you probably don't have SmartMIPS and should say N
2341 config CPU_MICROMIPS
2342 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2345 When this option is enabled the kernel will be built using the
2351 bool "Support for the MIPS SIMD Architecture"
2352 depends on CPU_SUPPORTS_MSA
2353 depends on MIPS_FP_SUPPORT
2354 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2356 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2357 and a set of SIMD instructions to operate on them. When this option
2358 is enabled the kernel will support allocating & switching MSA
2359 vector register contexts. If you know that your kernel will only be
2360 running on CPUs which do not support MSA or that your userland will
2361 not be making use of it then you may wish to say N here to reduce
2362 the size & complexity of your kernel.
2373 depends on !CPU_DIEI_BROKEN
2376 config CPU_DIEI_BROKEN
2382 config CPU_NO_LOAD_STORE_LR
2385 CPU lacks support for unaligned load and store instructions:
2386 LWL, LWR, SWL, SWR (Load/store word left/right).
2387 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2391 # Vectored interrupt mode is an R2 feature
2393 config CPU_MIPSR2_IRQ_VI
2397 # Extended interrupt mode is an R2 feature
2399 config CPU_MIPSR2_IRQ_EI
2404 depends on !CPU_R3000
2411 # Work around the "daddi" and "daddiu" CPU errata:
2413 # - The `daddi' instruction fails to trap on overflow.
2414 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2417 # - The `daddiu' instruction can produce an incorrect result.
2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2420 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2422 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2423 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2424 config CPU_DADDI_WORKAROUNDS
2427 # Work around certain R4000 CPU errata (as implemented by GCC):
2429 # - A double-word or a variable shift may give an incorrect result
2430 # if executed immediately after starting an integer division:
2431 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2433 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2436 # - A double-word or a variable shift may give an incorrect result
2437 # if executed while an integer multiplication is in progress:
2438 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2441 # - An integer division may give an incorrect result if started in
2442 # a delay slot of a taken branch or a jump:
2443 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2445 config CPU_R4000_WORKAROUNDS
2447 select CPU_R4400_WORKAROUNDS
2449 # Work around certain R4400 CPU errata (as implemented by GCC):
2451 # - A double-word or a variable shift may give an incorrect result
2452 # if executed immediately after starting an integer division:
2453 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2454 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2455 config CPU_R4400_WORKAROUNDS
2458 config CPU_R4X00_BUGS64
2460 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2462 config MIPS_ASID_SHIFT
2464 default 6 if CPU_R3000
2467 config MIPS_ASID_BITS
2469 default 0 if MIPS_ASID_BITS_VARIABLE
2470 default 6 if CPU_R3000
2473 config MIPS_ASID_BITS_VARIABLE
2476 config MIPS_CRC_SUPPORT
2479 # R4600 erratum. Due to the lack of errata information the exact
2480 # technical details aren't known. I've experimentally found that disabling
2481 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2483 config WAR_R4600_V1_INDEX_ICACHEOP
2486 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2488 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2489 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2490 # executed if there is no other dcache activity. If the dcache is
2491 # accessed for another instruction immediately preceding when these
2492 # cache instructions are executing, it is possible that the dcache
2493 # tag match outputs used by these cache instructions will be
2494 # incorrect. These cache instructions should be preceded by at least
2495 # four instructions that are not any kind of load or store
2498 # This is not allowed: lw
2502 # cache Hit_Writeback_Invalidate_D
2504 # This is allowed: lw
2509 # cache Hit_Writeback_Invalidate_D
2510 config WAR_R4600_V1_HIT_CACHEOP
2513 # Writeback and invalidate the primary cache dcache before DMA.
2515 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2516 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2517 # operate correctly if the internal data cache refill buffer is empty. These
2518 # CACHE instructions should be separated from any potential data cache miss
2519 # by a load instruction to an uncached address to empty the response buffer."
2520 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2522 config WAR_R4600_V2_HIT_CACHEOP
2525 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2526 # the line which this instruction itself exists, the following
2527 # operation is not guaranteed."
2529 # Workaround: do two phase flushing for Index_Invalidate_I
2530 config WAR_TX49XX_ICACHE_INDEX_INV
2533 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2534 # opposes it being called that) where invalid instructions in the same
2535 # I-cache line worth of instructions being fetched may case spurious
2537 config WAR_ICACHE_REFILLS
2540 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2541 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2542 config WAR_R10000_LLSC
2545 # 34K core erratum: "Problems Executing the TLBR Instruction"
2546 config WAR_MIPS34K_MISSED_ITLB
2550 # - Highmem only makes sense for the 32-bit kernel.
2551 # - The current highmem code will only work properly on physically indexed
2552 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2553 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2554 # moment we protect the user and offer the highmem option only on machines
2555 # where it's known to be safe. This will not offer highmem on a few systems
2556 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2557 # indexed CPUs but we're playing safe.
2558 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2559 # know they might have memory configurations that could make use of highmem
2563 bool "High Memory Support"
2564 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2567 config CPU_SUPPORTS_HIGHMEM
2570 config SYS_SUPPORTS_HIGHMEM
2573 config SYS_SUPPORTS_SMARTMIPS
2576 config SYS_SUPPORTS_MICROMIPS
2579 config SYS_SUPPORTS_MIPS16
2582 This option must be set if a kernel might be executed on a MIPS16-
2583 enabled CPU even if MIPS16 is not actually being used. In other
2584 words, it makes the kernel MIPS16-tolerant.
2586 config CPU_SUPPORTS_MSA
2589 config ARCH_FLATMEM_ENABLE
2591 depends on !NUMA && !CPU_LOONGSON2EF
2593 config ARCH_SPARSEMEM_ENABLE
2598 depends on SYS_SUPPORTS_NUMA
2600 select HAVE_SETUP_PER_CPU_AREA
2601 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2603 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2604 Access). This option improves performance on systems with more
2605 than two nodes; on two node systems it is generally better to
2606 leave it disabled; on single node systems leave this option
2609 config SYS_SUPPORTS_NUMA
2612 config HAVE_ARCH_NODEDATA_EXTENSION
2616 bool "Relocatable kernel"
2617 depends on SYS_SUPPORTS_RELOCATABLE
2618 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2619 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2620 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2621 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2624 This builds a kernel image that retains relocation information
2625 so it can be loaded someplace besides the default 1MB.
2626 The relocations make the kernel binary about 15% larger,
2627 but are discarded at runtime
2629 config RELOCATION_TABLE_SIZE
2630 hex "Relocation table size"
2631 depends on RELOCATABLE
2632 range 0x0 0x01000000
2633 default "0x00200000" if CPU_LOONGSON64
2634 default "0x00100000"
2636 A table of relocation data will be appended to the kernel binary
2637 and parsed at boot to fix up the relocated kernel.
2639 This option allows the amount of space reserved for the table to be
2640 adjusted, although the default of 1Mb should be ok in most cases.
2642 The build will fail and a valid size suggested if this is too small.
2644 If unsure, leave at the default value.
2646 config RANDOMIZE_BASE
2647 bool "Randomize the address of the kernel image"
2648 depends on RELOCATABLE
2650 Randomizes the physical and virtual address at which the
2651 kernel image is loaded, as a security feature that
2652 deters exploit attempts relying on knowledge of the location
2653 of kernel internals.
2655 Entropy is generated using any coprocessor 0 registers available.
2657 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2661 config RANDOMIZE_BASE_MAX_OFFSET
2662 hex "Maximum kASLR offset" if EXPERT
2663 depends on RANDOMIZE_BASE
2664 range 0x0 0x40000000 if EVA || 64BIT
2665 range 0x0 0x08000000
2666 default "0x01000000"
2668 When kASLR is active, this provides the maximum offset that will
2669 be applied to the kernel image. It should be set according to the
2670 amount of physical RAM available in the target system minus
2671 PHYSICAL_START and must be a power of 2.
2673 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2674 EVA or 64-bit. The default is 16Mb.
2681 config HW_PERF_EVENTS
2682 bool "Enable hardware performance counter support for perf events"
2683 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2686 Enable hardware performance counter support for perf events. If
2687 disabled, perf events will use software events only.
2690 bool "Enable DMI scanning"
2691 depends on MACH_LOONGSON64
2692 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2695 Enabled scanning of DMI to identify machine quirks. Say Y
2696 here unless you have verified that your setup is not
2697 affected by entries in the DMI blacklist. Required by PNP
2701 bool "Multi-Processing support"
2702 depends on SYS_SUPPORTS_SMP
2704 This enables support for systems with more than one CPU. If you have
2705 a system with only one CPU, say N. If you have a system with more
2706 than one CPU, say Y.
2708 If you say N here, the kernel will run on uni- and multiprocessor
2709 machines, but will use only one CPU of a multiprocessor machine. If
2710 you say Y here, the kernel will run on many, but not all,
2711 uniprocessor machines. On a uniprocessor machine, the kernel
2712 will run faster if you say N here.
2714 People using multiprocessor machines who say Y here should also say
2715 Y to "Enhanced Real Time Clock Support", below.
2717 See also the SMP-HOWTO available at
2718 <https://www.tldp.org/docs.html#howto>.
2720 If you don't know what to do here, say N.
2723 bool "Support for hot-pluggable CPUs"
2724 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2726 Say Y here to allow turning CPUs off and on. CPUs can be
2727 controlled through /sys/devices/system/cpu.
2728 (Note: power management support will enable this option
2729 automatically on SMP systems. )
2730 Say N if you want to disable CPU hotplug.
2735 config SYS_SUPPORTS_MIPS_CPS
2738 config SYS_SUPPORTS_SMP
2741 config NR_CPUS_DEFAULT_4
2744 config NR_CPUS_DEFAULT_8
2747 config NR_CPUS_DEFAULT_16
2750 config NR_CPUS_DEFAULT_32
2753 config NR_CPUS_DEFAULT_64
2757 int "Maximum number of CPUs (2-256)"
2760 default "4" if NR_CPUS_DEFAULT_4
2761 default "8" if NR_CPUS_DEFAULT_8
2762 default "16" if NR_CPUS_DEFAULT_16
2763 default "32" if NR_CPUS_DEFAULT_32
2764 default "64" if NR_CPUS_DEFAULT_64
2766 This allows you to specify the maximum number of CPUs which this
2767 kernel will support. The maximum supported value is 32 for 32-bit
2768 kernel and 64 for 64-bit kernels; the minimum value which makes
2769 sense is 1 for Qemu (useful only for kernel debugging purposes)
2770 and 2 for all others.
2772 This is purely to save memory - each supported CPU adds
2773 approximately eight kilobytes to the kernel image. For best
2774 performance should round up your number of processors to the next
2777 config MIPS_PERF_SHARED_TC_COUNTERS
2780 config MIPS_NR_CPU_NR_MAP_1024
2783 config MIPS_NR_CPU_NR_MAP
2786 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2787 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2790 # Timer Interrupt Frequency Configuration
2794 prompt "Timer frequency"
2797 Allows the configuration of the timer frequency.
2800 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2803 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2806 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2809 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2812 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2815 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2818 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2821 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2825 config SYS_SUPPORTS_24HZ
2828 config SYS_SUPPORTS_48HZ
2831 config SYS_SUPPORTS_100HZ
2834 config SYS_SUPPORTS_128HZ
2837 config SYS_SUPPORTS_250HZ
2840 config SYS_SUPPORTS_256HZ
2843 config SYS_SUPPORTS_1000HZ
2846 config SYS_SUPPORTS_1024HZ
2849 config SYS_SUPPORTS_ARBIT_HZ
2851 default y if !SYS_SUPPORTS_24HZ && \
2852 !SYS_SUPPORTS_48HZ && \
2853 !SYS_SUPPORTS_100HZ && \
2854 !SYS_SUPPORTS_128HZ && \
2855 !SYS_SUPPORTS_250HZ && \
2856 !SYS_SUPPORTS_256HZ && \
2857 !SYS_SUPPORTS_1000HZ && \
2858 !SYS_SUPPORTS_1024HZ
2864 default 100 if HZ_100
2865 default 128 if HZ_128
2866 default 250 if HZ_250
2867 default 256 if HZ_256
2868 default 1000 if HZ_1000
2869 default 1024 if HZ_1024
2872 def_bool HIGH_RES_TIMERS
2874 config ARCH_SUPPORTS_KEXEC
2877 config ARCH_SUPPORTS_CRASH_DUMP
2880 config PHYSICAL_START
2881 hex "Physical address where the kernel is loaded"
2882 default "0xffffffff84000000"
2883 depends on CRASH_DUMP
2885 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2886 If you plan to use kernel for capturing the crash dump change
2887 this value to start of the reserved region (the "X" value as
2888 specified in the "crashkernel=YM@XM" command line boot parameter
2889 passed to the panic-ed kernel).
2891 config MIPS_O32_FP64_SUPPORT
2892 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2893 depends on 32BIT || MIPS32_O32
2895 When this is enabled, the kernel will support use of 64-bit floating
2896 point registers with binaries using the O32 ABI along with the
2897 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2898 32-bit MIPS systems this support is at the cost of increasing the
2899 size and complexity of the compiled FPU emulator. Thus if you are
2900 running a MIPS32 system and know that none of your userland binaries
2901 will require 64-bit floating point, you may wish to reduce the size
2902 of your kernel & potentially improve FP emulation performance by
2905 Although binutils currently supports use of this flag the details
2906 concerning its effect upon the O32 ABI in userland are still being
2907 worked on. In order to avoid userland becoming dependent upon current
2908 behaviour before the details have been finalised, this option should
2909 be considered experimental and only enabled by those working upon
2917 select OF_EARLY_FLATTREE
2927 prompt "Kernel appended dtb support" if USE_OF
2928 default MIPS_NO_APPENDED_DTB
2930 config MIPS_NO_APPENDED_DTB
2933 Do not enable appended dtb support.
2935 config MIPS_ELF_APPENDED_DTB
2938 With this option, the boot code will look for a device tree binary
2939 DTB) included in the vmlinux ELF section .appended_dtb. By default
2940 it is empty and the DTB can be appended using binutils command
2943 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2945 This is meant as a backward compatibility convenience for those
2946 systems with a bootloader that can't be upgraded to accommodate
2947 the documented boot protocol using a device tree.
2949 config MIPS_RAW_APPENDED_DTB
2950 bool "vmlinux.bin or vmlinuz.bin"
2952 With this option, the boot code will look for a device tree binary
2953 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2954 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2956 This is meant as a backward compatibility convenience for those
2957 systems with a bootloader that can't be upgraded to accommodate
2958 the documented boot protocol using a device tree.
2960 Beware that there is very little in terms of protection against
2961 this option being confused by leftover garbage in memory that might
2962 look like a DTB header after a reboot if no actual DTB is appended
2963 to vmlinux.bin. Do not leave this option active in a production kernel
2964 if you don't intend to always append a DTB.
2968 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2969 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2970 !MACH_LOONGSON64 && !MIPS_MALTA && \
2972 default MIPS_CMDLINE_FROM_BOOTLOADER
2974 config MIPS_CMDLINE_FROM_DTB
2976 bool "Dtb kernel arguments if available"
2978 config MIPS_CMDLINE_DTB_EXTEND
2980 bool "Extend dtb kernel arguments with bootloader arguments"
2982 config MIPS_CMDLINE_FROM_BOOTLOADER
2983 bool "Bootloader kernel arguments if available"
2985 config MIPS_CMDLINE_BUILTIN_EXTEND
2986 depends on CMDLINE_BOOL
2987 bool "Extend builtin kernel arguments with bootloader arguments"
2992 config LOCKDEP_SUPPORT
2996 config STACKTRACE_SUPPORT
3000 config PGTABLE_LEVELS
3002 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
3003 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3006 config MIPS_AUTO_PFN_OFFSET
3009 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3011 config PCI_DRIVERS_GENERIC
3012 select PCI_DOMAINS_GENERIC if PCI
3015 config PCI_DRIVERS_LEGACY
3016 def_bool !PCI_DRIVERS_GENERIC
3017 select NO_GENERIC_PCI_IOPORT_MAP
3018 select PCI_DOMAINS if PCI
3021 # ISA support is now enabled via select. Too many systems still have the one
3022 # or other ISA chip on the board that users don't know about so don't expect
3023 # users to choose the right thing ...
3029 bool "TURBOchannel support"
3030 depends on MACH_DECSTATION
3032 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3033 processors. TURBOchannel programming specifications are available
3035 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
3037 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3038 Linux driver support status is documented at:
3039 <http://www.linux-mips.org/wiki/DECstation>
3045 config ARCH_MMAP_RND_BITS_MIN
3049 config ARCH_MMAP_RND_BITS_MAX
3053 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3056 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3063 select MIPS_EXTERNAL_TIMER
3069 config MIPS32_COMPAT
3076 bool "Kernel support for o32 binaries"
3078 select ARCH_WANT_OLD_COMPAT_IPC
3080 select MIPS32_COMPAT
3082 Select this option if you want to run o32 binaries. These are pure
3083 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3084 existing binaries are in this format.
3089 bool "Kernel support for n32 binaries"
3091 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3093 select MIPS32_COMPAT
3095 Select this option if you want to run n32 binaries. These are
3096 64-bit binaries using 32-bit quantities for addressing and certain
3097 data that would normally be 64-bit. They are used in special
3102 config CC_HAS_MNO_BRANCH_LIKELY
3104 depends on $(cc-option,-mno-branch-likely)
3106 # https://github.com/llvm/llvm-project/issues/61045
3107 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3108 def_bool y if CC_IS_CLANG
3110 menu "Power management options"
3112 config ARCH_HIBERNATION_POSSIBLE
3114 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3116 config ARCH_SUSPEND_POSSIBLE
3118 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3120 source "kernel/power/Kconfig"
3124 config MIPS_EXTERNAL_TIMER
3127 menu "CPU Power Management"
3129 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3130 source "drivers/cpufreq/Kconfig"
3131 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3133 source "drivers/cpuidle/Kconfig"
3137 source "arch/mips/kvm/Kconfig"
3139 source "arch/mips/vdso/Kconfig"