1 ======================================
2 Coresight - HW Assisted Tracing on ARM
3 ======================================
5 :Author: Mathieu Poirier <mathieu.poirier@linaro.org>
6 :Date: September 11th, 2014
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
12 based SoC. It includes solutions for JTAG and HW assisted tracing. This
13 document is concerned with the latter.
15 HW assisted tracing is becoming increasingly useful when dealing with systems
16 that have many SoCs and other components like GPU and DMA engines. ARM has
17 developed a HW assisted tracing solution by means of different components, each
18 being added to a design at synthesis time to cater to specific tracing needs.
19 Components are generally categorised as source, link and sinks and are
20 (usually) discovered using the AMBA bus.
22 "Sources" generate a compressed stream representing the processor instruction
23 path based on tracing scenarios as configured by users. From there the stream
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
26 implementation, either storing the compressed stream in a memory buffer or
27 creating an interface to the outside world where data can be transferred to a
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
32 *****************************************************************
33 **************************** AMBA AXI ****************************===||
34 ***************************************************************** ||
37 0000000 ::::: 0000000 ::::: ::::: @@@@@@@ ||||||||||||
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
41 | # ETM # ::::: | # PTM # ::::: ::::: @ |
42 | ##### ^ ^ | ##### ^ ! ^ ! . | |||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
44 | | # | ! | | # | ! | ! . | |||||||||
45 | | . | ! | | . | ! | ! . | | |
46 | | . | ! | | . | ! | ! . | | *
47 | | . | ! | | . | ! | ! . | | SWD/
48 | | . | ! | | . | ! | ! . | | JTAG
49 *****************************************************************<-|
50 *************************** AMBA Debug APB ************************
51 *****************************************************************
54 *****************************************************************
55 ******************** Cross Trigger Matrix (CTM) *******************
56 *****************************************************************
59 *****************************************************************
60 ****************** AMBA Advanced Trace Bus (ATB) ******************
61 *****************************************************************
63 | * ===== F =====<---------|
64 | ::::::::: ==== U ====
65 |-->:: CTI ::<!! === N ===
68 | ! &&&&&&&&& IIIIIII == L ==
69 |------>&& ETB &&<......II I =======
72 | ! I REP I<..........
74 | !!>&&&&&&&&& II I *Source: ARM ltd.
75 |------>& TPIU &<......II I DAP = Debug Access Port
76 &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell
77 ; PTM = Program Trace Macrocell
78 ; CTI = Cross Trigger Interface
79 * ETB = Embedded Trace Buffer
80 To trace port TPIU= Trace Port Interface Unit
81 SWD = Serial Wire Debug
83 While on target configuration of the components is done via the APB bus,
84 all trace data are carried out-of-band on the ATB bus. The CTM provides
85 a way to aggregate and distribute signals between CoreSight components.
87 The coresight framework provides a central point to represent, configure and
88 manage coresight devices on a platform. This first implementation centers on
89 the basic tracing functionality, enabling components such ETM/PTM, funnel,
90 replicator, TMC, TPIU and ETB. Future work will enable more
91 intricate IP blocks such as STM and CTI.
94 Acronyms and Classification
95 ---------------------------
100 Program Trace Macrocell
102 Embedded Trace Macrocell
104 System trace Macrocell
106 Embedded Trace Buffer
108 Instrumentation Trace Macrocell
110 Trace Port Interface Unit
112 Trace Memory Controller, configured as Embedded Trace Router
114 Trace Memory Controller, configured as Embedded Trace FIFO
116 Cross Trigger Interface
121 ETMv3.x ETMv4, PTMv1.0, PTMv1.1, STM, STM500, ITM
123 Funnel, replicator (intelligent or not), TMC-ETR
125 ETBv1.0, ETB1.1, TPIU, TMC-ETF
133 See Documentation/devicetree/bindings/arm/coresight.txt for details.
135 As of this writing drivers for ITM, STMs and CTIs are not provided but are
136 expected to be added as the solution matures.
139 Framework and implementation
140 ----------------------------
142 The coresight framework provides a central point to represent, configure and
143 manage coresight devices on a platform. Any coresight compliant device can
144 register with the framework for as long as they use the right APIs:
146 .. c:function:: struct coresight_device *coresight_register(struct coresight_desc *desc);
147 .. c:function:: void coresight_unregister(struct coresight_device *csdev);
149 The registering function is taking a ``struct coresight_desc *desc`` and
150 register the device with the core framework. The unregister function takes
151 a reference to a ``struct coresight_device *csdev`` obtained at registration time.
153 If everything goes well during the registration process the new devices will
154 show up under /sys/bus/coresight/devices, as showns here for a TC2 platform::
156 root:~# ls /sys/bus/coresight/devices/
157 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
158 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
161 The functions take a ``struct coresight_device``, which looks like this::
163 struct coresight_desc {
164 enum coresight_dev_type type;
165 struct coresight_dev_subtype subtype;
166 const struct coresight_ops *ops;
167 struct coresight_platform_data *pdata;
169 const struct attribute_group **groups;
173 The "coresight_dev_type" identifies what the device is, i.e, source link or
174 sink while the "coresight_dev_subtype" will characterise that type further.
176 The ``struct coresight_ops`` is mandatory and will tell the framework how to
177 perform base operations related to the components, each component having
178 a different set of requirement. For that ``struct coresight_ops_sink``,
179 ``struct coresight_ops_link`` and ``struct coresight_ops_source`` have been
182 The next field ``struct coresight_platform_data *pdata`` is acquired by calling
183 ``of_get_coresight_platform_data()``, as part of the driver's _probe routine and
184 ``struct device *dev`` gets the device reference embedded in the ``amba_device``::
186 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
190 drvdata->dev = &adev->dev;
194 Specific class of device (source, link, or sink) have generic operations
195 that can be performed on them (see ``struct coresight_ops``). The ``**groups``
196 is a list of sysfs entries pertaining to operations
197 specific to that component only. "Implementation defined" customisations are
198 expected to be accessed and controlled using those entries.
203 The devices that appear on the "coresight" bus were named the same as their
204 parent devices, i.e, the real devices that appears on AMBA bus or the platform bus.
205 Thus the names were based on the Linux Open Firmware layer naming convention,
206 which follows the base physical address of the device followed by the device
209 root:~# ls /sys/bus/coresight/devices/
210 20010000.etf 20040000.funnel 20100000.stm 22040000.etm
211 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu
212 20070000.etr 20120000.replicator 220c0000.funnel
213 23040000.etm 23140000.etm 23340000.etm
215 However, with the introduction of ACPI support, the names of the real
216 devices are a bit cryptic and non-obvious. Thus, a new naming scheme was
217 introduced to use more generic names based on the type of the device. The
218 following rules apply::
220 1) Devices that are bound to CPUs, are named based on the CPU logical
223 e.g, ETM bound to CPU0 is named "etm0"
225 2) All other devices follow a pattern, "<device_type_prefix>N", where :
227 <device_type_prefix> - A prefix specific to the type of the device
228 N - a sequential number assigned based on the order
231 e.g, tmc_etf0, tmc_etr0, funnel0, funnel1
233 Thus, with the new scheme the devices could appear as ::
235 root:~# ls /sys/bus/coresight/devices/
236 etm0 etm1 etm2 etm3 etm4 etm5 funnel0
237 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
239 Some of the examples below might refer to old naming scheme and some
240 to the newer scheme, to give a confirmation that what you see on your
241 system is not unexpected. One must use the "names" as they appear on
242 the system under specified locations.
244 Topology Representation
245 -----------------------
247 Each CoreSight component has a ``connections`` directory which will contain
248 links to other CoreSight components. This allows the user to explore the trace
249 topology and for larger systems, determine the most appropriate sink for a
250 given source. The connection information can also be used to establish
251 which CTI devices are connected to a given component. This directory contains a
252 ``nr_links`` attribute detailing the number of links in the directory.
254 For an ETM source, in this case ``etm0`` on a Juno platform, a typical
255 arrangement will be::
257 linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections
258 <file details> cti_cpu0 -> ../../../23020000.cti/cti_cpu0
259 <file details> nr_links
260 <file details> out:0 -> ../../../230c0000.funnel/funnel2
262 Following the out port to ``funnel2``::
264 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections
265 <file details> in:0 -> ../../../23040000.etm/etm0
266 <file details> in:1 -> ../../../23140000.etm/etm3
267 <file details> in:2 -> ../../../23240000.etm/etm4
268 <file details> in:3 -> ../../../23340000.etm/etm5
269 <file details> nr_links
270 <file details> out:0 -> ../../../20040000.funnel/funnel0
272 And again to ``funnel0``::
274 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections
275 <file details> in:0 -> ../../../220c0000.funnel/funnel1
276 <file details> in:1 -> ../../../230c0000.funnel/funnel2
277 <file details> nr_links
278 <file details> out:0 -> ../../../20010000.etf/tmc_etf0
280 Finding the first sink ``tmc_etf0``. This can be used to collect data
281 as a sink, or as a link to propagate further along the chain::
283 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections
284 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
285 <file details> in:0 -> ../../../20040000.funnel/funnel0
286 <file details> nr_links
287 <file details> out:0 -> ../../../20150000.funnel/funnel4
291 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections
292 <file details> in:0 -> ../../../20010000.etf/tmc_etf0
293 <file details> in:1 -> ../../../20140000.etf/tmc_etf1
294 <file details> nr_links
295 <file details> out:0 -> ../../../20120000.replicator/replicator0
297 and a ``replicator0``::
299 linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections
300 <file details> in:0 -> ../../../20150000.funnel/funnel4
301 <file details> nr_links
302 <file details> out:0 -> ../../../20030000.tpiu/tpiu0
303 <file details> out:1 -> ../../../20070000.etr/tmc_etr0
305 Arriving at the final sink in the chain, ``tmc_etr0``::
307 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections
308 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
309 <file details> in:0 -> ../../../20120000.replicator/replicator0
310 <file details> nr_links
312 As described below, when using sysfs it is sufficient to enable a sink and
313 a source for successful trace. The framework will correctly enable all
314 intermediate links as required.
316 Note: ``cti_sys0`` appears in two of the connections lists above.
317 CTIs can connect to multiple devices and are arranged in a star topology
318 via the CTM. See (Documentation/trace/coresight/coresight-ect.rst)
319 [#fourth]_ for further details.
320 Looking at this device we see 4 connections::
322 linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections
323 <file details> nr_links
324 <file details> stm0 -> ../../../20100000.stm/stm0
325 <file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0
326 <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0
327 <file details> tpiu0 -> ../../../20030000.tpiu/tpiu0
330 How to use the tracer modules
331 -----------------------------
333 There are two ways to use the Coresight framework:
335 1. using the perf cmd line tools.
336 2. interacting directly with the Coresight devices using the sysFS interface.
338 Preference is given to the former as using the sysFS interface
339 requires a deep understanding of the Coresight HW. The following sections
340 provide details on using both methods.
342 1) Using the sysFS interface:
344 Before trace collection can start, a coresight sink needs to be identified.
345 There is no limit on the amount of sinks (nor sources) that can be enabled at
346 any given moment. As a generic operation, all device pertaining to the sink
347 class will have an "active" entry in sysfs::
349 root:/sys/bus/coresight/devices# ls
350 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
351 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
352 root:/sys/bus/coresight/devices# ls 20010000.etb
353 enable_sink status trigger_cntr
354 root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink
355 root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink
357 root:/sys/bus/coresight/devices#
359 At boot time the current etm3x driver will configure the first address
360 comparator with "_stext" and "_etext", essentially tracing any instruction
361 that falls within that range. As such "enabling" a source will immediately
362 trigger a trace capture::
364 root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source
365 root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source
367 root:/sys/bus/coresight/devices# cat 20010000.etb/status
371 RAM wrt ptr: 0x19d3 <----- The write pointer is moving
376 root:/sys/bus/coresight/devices#
378 Trace collection is stopped the same way::
380 root:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source
381 root:/sys/bus/coresight/devices#
383 The content of the ETB buffer can be harvested directly from /dev::
385 root:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \
389 32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s
390 root:/sys/bus/coresight/devices#
392 The file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.
394 Following is a DS-5 output of an experimental loop that increments a variable up
395 to a certain value. The example is simple and yet provides a glimpse of the
396 wealth of possibilities that coresight provides.
400 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
401 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
402 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
403 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
404 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
405 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
406 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
407 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
408 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
409 Timestamp Timestamp: 17106715833
410 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]
411 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
412 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
413 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
414 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
415 Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4]
416 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
417 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
418 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
419 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
420 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
421 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
422 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
423 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
424 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
425 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
426 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
427 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
428 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
429 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
430 Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4]
431 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
432 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
433 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
434 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
435 Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1
436 Instruction 0 0x8026B564 E1A0100D false MOV r1,sp
437 Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0
438 Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f
439 Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4]
440 Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368
441 Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc]
442 Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0]
443 Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4
445 Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
446 Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
447 Timestamp Timestamp: 17107041535
449 2) Using perf framework:
451 Coresight tracers are represented using the Perf framework's Performance
452 Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of
453 controlling when tracing gets enabled based on when the process of interest is
454 scheduled. When configured in a system, Coresight PMUs will be listed when
455 queried by the perf command line tool:
457 linaro@linaro-nano:~$ ./perf list pmu
459 List of pre-defined events (to be used in -e):
461 cs_etm// [Kernel PMU event]
463 linaro@linaro-nano:~$
465 Regardless of the number of tracers available in a system (usually equal to the
466 amount of processor cores), the "cs_etm" PMU will be listed only once.
468 A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is
469 listed along with configuration options within forward slashes '/'. Since a
470 Coresight system will typically have more than one sink, the name of the sink to
471 work with needs to be specified as an event option.
472 On newer kernels the available sinks are listed in sysFS under
473 ($SYSFS)/bus/event_source/devices/cs_etm/sinks/::
475 root@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls
476 tmc_etf0 tmc_etr0 tpiu0
478 On older kernels, this may need to be found from the list of coresight devices,
479 available under ($SYSFS)/bus/coresight/devices/::
481 root:~# ls /sys/bus/coresight/devices/
482 etm0 etm1 etm2 etm3 etm4 etm5 funnel0
483 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
484 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
486 As mentioned above in section "Device Naming scheme", the names of the devices could
487 look different from what is used in the example above. One must use the device names
488 as it appears under the sysFS.
490 The syntax within the forward slashes '/' is important. The '@' character
491 tells the parser that a sink is about to be specified and that this is the sink
492 to use for the trace session.
494 More information on the above and other example on how to use Coresight with
495 the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub
496 repository [#third]_.
498 2.1) AutoFDO analysis using the perf tools:
500 perf can be used to record and analyze trace of programs.
502 Execution can be recorded using 'perf record' with the cs_etm event,
503 specifying the name of the sink to record to, e.g::
505 perf record -e cs_etm/@tmc_etr0/u --per-thread
507 The 'perf report' and 'perf script' commands can be used to analyze execution,
508 synthesizing instruction and branch events from the instruction trace.
509 'perf inject' can be used to replace the trace data with the synthesized events.
510 The --itrace option controls the type and frequency of synthesized events
511 (see perf documentation).
513 Note that only 64-bit programs are currently supported - further work is
514 required to support instruction decode of 32-bit Arm programs.
518 The kernel can be built to write the PID value into the PE ContextID registers.
519 For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may
520 implement Arm Virtualization Host Extensions (VHE), which the kernel can
521 run at EL2 as a virtualisation host; in this case, the PID value is stored in
524 perf provides PMU formats that program the ETM to insert these values into the
525 trace data; the PMU formats are defined as below:
527 "contextid1": Available on both EL1 kernel and EL2 kernel. When the
528 kernel is running at EL1, "contextid1" enables the PID
529 tracing; when the kernel is running at EL2, this enables
530 tracing the PID of guest applications.
532 "contextid2": Only usable when the kernel is running at EL2. When
533 selected, enables PID tracing on EL2 kernel.
535 "contextid": Will be an alias for the option that enables PID
537 contextid == contextid1, on EL1 kernel.
538 contextid == contextid2, on EL2 kernel.
540 perf will always enable PID tracing at the relevant EL, this is accomplished by
541 automatically enable the "contextid" config - but for EL2 it is possible to make
542 specific adjustments using configs "contextid1" and "contextid2", E.g. if a user
543 wants to trace PIDs for both host and guest, the two configs "contextid1" and
544 "contextid2" can be set at the same time:
546 perf record -e cs_etm/contextid1,contextid2/u -- vm
549 Generating coverage files for Feedback Directed Optimization: AutoFDO
550 ---------------------------------------------------------------------
552 'perf inject' accepts the --itrace option in which case tracing data is
553 removed and replaced with the synthesized events. e.g.
556 perf inject --itrace --strip -i perf.data -o perf.data.new
558 Below is an example of using ARM ETM for autoFDO. It requires autofdo
559 (https://github.com/google/autofdo) and gcc version 5. The bubble
560 sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial).
563 $ gcc-5 -O3 sort.c -o sort
564 $ taskset -c 2 ./sort
565 Bubble sorting array of 30000 elements
568 $ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort
569 Bubble sorting array of 30000 elements
571 [ perf record: Woken up 35 times to write data ]
572 [ perf record: Captured and wrote 69.640 MB perf.data ]
574 $ perf inject -i perf.data -o inj.data --itrace=il64 --strip
575 $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1
576 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
577 $ taskset -c 2 ./sort_autofdo
578 Bubble sorting array of 30000 elements
582 How to use the STM module
583 -------------------------
585 Using the System Trace Macrocell module is the same as the tracers - the only
586 difference is that clients are driving the trace capture rather
587 than the program flow through the code.
589 As with any other CoreSight component, specifics about the STM tracer can be
590 found in sysfs with more information on each entry being found in [#first]_::
592 root@genericarmv8:~# ls /sys/bus/coresight/devices/stm0
593 enable_source hwevent_select port_enable subsystem uevent
594 hwevent_enable mgmt port_select traceid
597 Like any other source a sink needs to be identified and the STM enabled before
600 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
601 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_source
603 From there user space applications can request and use channels using the devfs
604 interface provided for that purpose by the generic STM API::
606 root@genericarmv8:~# ls -l /dev/stm0
607 crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0
610 Details on how to use the generic STM API can be found here:
611 - Documentation/trace/stm.rst [#second]_.
613 The CTI & CTM Modules
614 ---------------------
616 The CTI (Cross Trigger Interface) provides a set of trigger signals between
617 individual CTIs and components, and can propagate these between all CTIs via
618 channels on the CTM (Cross Trigger Matrix).
620 A separate documentation file is provided to explain the use of these devices.
621 (Documentation/trace/coresight/coresight-ect.rst) [#fourth]_.
623 CoreSight System Configuration
624 ------------------------------
626 CoreSight components can be complex devices with many programming options.
627 Furthermore, components can be programmed to interact with each other across the
630 A CoreSight System Configuration manager is provided to allow these complex programming
631 configurations to be selected and used easily from perf and sysfs.
633 See the separate document for further information.
634 (Documentation/trace/coresight/coresight-config.rst) [#fifth]_.
637 .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
639 .. [#second] Documentation/trace/stm.rst
641 .. [#third] https://github.com/Linaro/perf-opencsd
643 .. [#fourth] Documentation/trace/coresight/coresight-ect.rst
645 .. [#fifth] Documentation/trace/coresight/coresight-config.rst