4 This is a port of Linux to the OpenRISC class of microprocessors; the initial
5 target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
7 For information about OpenRISC processors and ongoing development:
9 website http://openrisc.io
10 email openrisc@lists.librecores.org
12 ---------------------------------------------------------------------
14 Build instructions for OpenRISC toolchain and Linux
15 ===================================================
17 In order to build and run Linux for OpenRISC, you'll need at least a basic
18 toolchain and, perhaps, the architectural simulator. Steps to get these bits
19 in place are outlined here.
23 Toolchain binaries can be obtained from openrisc.io or our github releases page.
24 Instructions for building the different toolchains can be found on openrisc.io
25 or Stafford's toolchain build and release scripts.
27 binaries https://github.com/openrisc/or1k-gcc/releases
28 toolchains https://openrisc.io/software
29 building https://github.com/stffrdhrn/or1k-toolchain-build
33 Build the Linux kernel as usual
35 make ARCH=openrisc defconfig
38 3) Running on FPGA (optional)
40 The OpenRISC community typically uses FuseSoC to manage building and programming
41 an SoC into an FPGA. The below is an example of programming a De0 Nano
42 development board with the OpenRISC SoC. During the build FPGA RTL is code
43 downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
44 tools. Binaries are loaded onto the board with openocd.
46 git clone https://github.com/olofk/fusesoc
51 fusesoc build de0_nano
54 openocd -f interface/altera-usb-blaster.cfg \
55 -f board/or1k_generic.cfg
59 > halt; load_image vmlinux ; reset
61 4) Running on a Simulator (optional)
63 QEMU is a processor emulator which we recommend for simulating the OpenRISC
64 platform. Please follow the OpenRISC instructions on the QEMU website to get
65 Linux running on QEMU. You can build QEMU yourself, but your Linux distribution
66 likely provides binary packages to support OpenRISC.
68 qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC
70 ---------------------------------------------------------------------
75 In the code, the following particles are used on symbols to limit the scope
76 to more or less specific processor implementations:
78 openrisc: the OpenRISC class of processors
79 or1k: the OpenRISC 1000 family of processors
80 or1200: the OpenRISC 1200 processor
82 ---------------------------------------------------------------------
87 18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
88 initial port of linux to OpenRISC/or32 architecture.
89 all the core stuff is implemented and seams usable.
91 08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
92 complete change of TLB miss handling.
93 rewrite of exceptions handling.
94 fully functional sash-3.6 in default initrd.
95 a much improved version with changes all around.
97 10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
98 alot of bugfixes all over.
99 ethernet support, functional http and telnet servers.
100 running many standard linux apps.
102 26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
105 30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
106 lots of bugfixes and enhancments.
107 added opencores framebuffer driver.
109 09. 10. 2010 Jonas Bonn (jonas@southpole.se)
110 major rewrite to bring up to par with upstream Linux 2.6.36