1 .. SPDX-License-Identifier: GPL-2.0
3 =======================================
4 QLogic QLGE 10Gb Ethernet device driver
5 =======================================
7 This driver use drgn and devlink for debugging.
9 Dump kernel data structures in drgn
10 -----------------------------------
12 To dump kernel data structures, the following Python script can be used
15 .. code-block:: python
18 """the alignment a should be a power of 2
21 return (x+ mask) & ~mask
23 def struct_size(struct_type):
24 struct_str = "struct {}".format(struct_type)
25 return sizeof(Object(prog, struct_str, address=0x0))
27 def netdev_priv(netdevice):
29 return netdevice.value_() + align(struct_size("net_device"), NETDEV_ALIGN)
33 netdevices = prog['init_net'].dev_base_head.address_of_()
34 for netdevice in list_for_each_entry("struct net_device", netdevices, "dev_list"):
35 if netdevice.name.string_().decode('ascii') == name:
38 ql_adapter = Object(prog, "struct ql_adapter", address=netdev_priv(qlge_device))
40 The struct ql_adapter will be printed in drgn as follows,
44 .ricb = (struct ricb){
47 .mask = (__le16)26637,
48 .hash_cq_id = (u8 [1024]){ 172, 142, 255, 255 },
49 .ipv6_hash_key = (__le32 [10]){},
50 .ipv4_hash_key = (__le32 [4]){},
52 .flags = (unsigned long)0,
54 .nic_stats = (struct nic_stats){
57 .tx_mcast_pkts = (u64)0,
58 .tx_bcast_pkts = (u64)0,
59 .tx_ucast_pkts = (u64)0,
60 .tx_ctl_pkts = (u64)0,
61 .tx_pause_pkts = (u64)0,
64 .active_vlans = (unsigned long [64]){
65 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52780853100545, 18446744073709551615,
66 18446619461681283072, 0, 42949673024, 2147483647,
68 .rx_ring = (struct rx_ring [17]){
70 .cqicb = (struct cqicb){
79 .cq_base = (void *)0x0,
80 .cq_base_dma = (dma_addr_t)0,
90 And the coredump obtained via devlink in json format looks like,
94 $ devlink health dump show DEVICE reporter coredump -p -j
98 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
102 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
106 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
111 "values": [ 0,0,0,0 ]
115 When the module parameter qlge_force_coredump is set to be true, the MPI
116 RISC reset before coredumping. So coredumping will much longer since
117 devlink tool has to wait for 5 secs for the resetting to be