1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
12 working modes a dpll can support, differentiates if and how dpll selects
13 one of its inputs to syntonize with it, valid values for DPLL_A_MODE
18 doc: input can be only selected by sending a request to dpll
22 doc: highest prio input pin auto selected by dpll
28 provides information of dpll device lock status, valid values for
29 DPLL_A_LOCK_STATUS attribute
34 dpll was not yet locked to any valid input (or forced by setting
35 DPLL_A_MODE to DPLL_MODE_DETACHED)
40 dpll is locked to a valid signal, but no holdover available
44 dpll is locked and holdover acquired
48 dpll is in holdover state - lost a valid lock or was forced
49 by disconnecting all the pins (latter possible only
50 when dpll lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
51 if dpll lock-state was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the
52 dpll's lock-state shall remain DPLL_LOCK_STATUS_UNLOCKED)
56 name: lock-status-error
58 if previous status change was done due to a failure, this provides
59 information of dpll device lock status error.
60 Valid values for DPLL_A_LOCK_STATUS_ERROR attribute
65 dpll device lock status was changed without any error
70 dpll device lock status was changed due to undefined error.
71 Driver fills this value up in case it is not able
72 to obtain suitable exact error type.
76 dpll device lock status was changed because of associated
78 This may happen for example if dpll device was previously
79 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
81 name: fractional-frequency-offset-too-high
83 the FFO (Fractional Frequency Offset) between the RX and TX
84 symbol rate on the media got too high.
85 This may happen for example if dpll device was previously
86 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
93 temperature divider allowing userspace to calculate the
94 temperature as float with three digit decimal precision.
95 Value of (DPLL_A_TEMP / DPLL_TEMP_DIVIDER) is integer part of
97 Value of (DPLL_A_TEMP % DPLL_TEMP_DIVIDER) is fractional part of
102 doc: type of dpll, valid values for DPLL_A_TYPE attribute
106 doc: dpll produces Pulse-Per-Second signal
110 doc: dpll drives the Ethernet Equipment Clock
116 defines possible types of a pin, valid values for DPLL_A_PIN_TYPE
121 doc: aggregates another layer of selectable pins
128 doc: ethernet port PHY's recovered clock
131 doc: device internal oscillator
134 doc: GNSS recovered clock
140 defines possible direction of a pin, valid values for
141 DPLL_A_PIN_DIRECTION attribute
145 doc: pin used as a input of a signal
149 doc: pin used to output the signal
153 name: pin-frequency-1-hz
157 name: pin-frequency-10-khz
161 name: pin-frequency-77_5-khz
165 name: pin-frequency-10-mhz
171 defines possible states of a pin, valid values for
172 DPLL_A_PIN_STATE attribute
176 doc: pin connected, active input of phase locked loop
180 doc: pin disconnected, not considered as a valid input
183 doc: pin enabled for automatic input selection
187 name: pin-capabilities
189 defines possible capabilities of a pin, valid flags on
190 DPLL_A_PIN_CAPABILITIES attribute
193 name: direction-can-change
194 doc: pin direction can be changed
196 name: priority-can-change
197 doc: pin priority can be changed
199 name: state-can-change
200 doc: pin state can be changed
203 name: phase-offset-divider
206 phase offset divider allows userspace to calculate a value of
207 measured signal phase difference between a pin and dpll device
208 as a fractional value with three digit decimal precision.
209 Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
210 integer part of a measured phase offset value.
211 Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
212 fractional part of a measured phase offset value.
252 name: lock-status-error
254 enum: lock-status-error
257 enum-name: dpll_a_pin
295 name: frequency-supported
298 nested-attributes: frequency-range
315 enum: pin-capabilities
320 nested-attributes: pin-parent-device
325 nested-attributes: pin-parent-pin
327 name: phase-adjust-min
330 name: phase-adjust-max
339 name: fractional-frequency-offset
342 The FFO (Fractional Frequency Offset) between the RX and TX
343 symbol rate on the media associated with the pin:
344 (rx_frequency-tx_frequency)/rx_frequency
345 Value is in PPM (parts per million).
346 This may be implemented for example for pin of type
347 PIN_TYPE_SYNCE_ETH_PORT.
349 name: pin-parent-device
371 name: frequency-range
385 Get id of dpll device that matches given attributes
387 flags: [ admin-perm ]
391 post: dpll-unlock-doit
404 Get list of DPLL devices (dump) or attributes of a single dpll device
406 flags: [ admin-perm ]
431 doc: Set attributes for a DPLL device
433 flags: [ admin-perm ]
442 name: device-create-ntf
443 doc: Notification about device appearing
447 name: device-delete-ntf
448 doc: Notification about device disappearing
452 name: device-change-ntf
453 doc: Notification about device configuration being changed
459 Get id of a pin that matches given attributes
461 flags: [ admin-perm ]
465 post: dpll-unlock-doit
481 Get list of pins and its attributes.
482 - dump request without any attributes given - list all the pins in the
484 - dump request with target dpll - list all the pins registered with
486 - do request with target dpll and target pin - single pin attributes
488 flags: [ admin-perm ]
491 pre: dpll-pin-pre-doit
492 post: dpll-pin-post-doit
504 - frequency-supported
511 - fractional-frequency-offset
521 doc: Set attributes of a target pin
523 flags: [ admin-perm ]
526 pre: dpll-pin-pre-doit
527 post: dpll-pin-post-doit
540 doc: Notification about pin appearing
545 doc: Notification about pin disappearing
550 doc: Notification about pin configuration being changed