Documentation/hwmon/max16601.rst

   1 .. SPDX-License-Identifier: GPL-2.0
   2
   3 Kernel driver max16601
   4 ======================
   5
   6 Supported chips:
   7
   8   * Maxim MAX16508
   9
  10     Prefix: 'max16508'
  11
  12     Addresses scanned: -
  13
  14     Datasheet: Not published
  15
  16   * Maxim MAX16601
  17
  18     Prefix: 'max16601'
  19
  20     Addresses scanned: -
  21
  22     Datasheet: Not published
  23
  24   * Maxim MAX16602
  25
  26     Prefix: 'max16602'
  27
  28     Addresses scanned: -
  29
  30     Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf
  31
  32 Author: Guenter Roeck <linux@roeck-us.net>
  33
  34
  35 Description
  36 -----------
  37
  38 This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator
  39 as well as the MAX16601 VR13.HC Dual-Output Voltage Regulator chipsets.
  40
  41 The driver is a client driver to the core PMBus driver.
  42 Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
  43
  44
  45 Usage Notes
  46 -----------
  47
  48 This driver does not auto-detect devices. You will have to instantiate the
  49 devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for
  50 details.
  51
  52
  53 Platform data support
  54 ---------------------
  55
  56 The driver supports standard PMBus driver platform data.
  57
  58
  59 Sysfs entries
  60 -------------
  61
  62 The following attributes are supported.
  63
  64 =============================== ===============================================
  65 in1_label                       "vin1"
  66 in1_input                       VCORE input voltage.
  67 in1_alarm                       Input voltage alarm.
  68
  69 in2_label                       "vout1"
  70 in2_input                       VCORE output voltage.
  71 in2_alarm                       Output voltage alarm.
  72
  73 curr1_label                     "iin1"
  74 curr1_input                     VCORE input current, derived from duty cycle
  75                                 and output current.
  76 curr1_max                       Maximum input current.
  77 curr1_max_alarm                 Current high alarm.
  78
  79 curr[P+2]_label                 "iin1.P"
  80 curr[P+2]_input                 VCORE phase P input current.
  81
  82 curr[N+2]_label                 "iin2"
  83 curr[N+2]_input                 VCORE input current, derived from sensor
  84                                 element.
  85                                 'N' is the number of enabled/populated phases.
  86
  87 curr[N+3]_label                 "iin3"
  88 curr[N+3]_input                 VSA input current.
  89
  90 curr[N+4]_label                 "iout1"
  91 curr[N+4]_input                 VCORE output current.
  92 curr[N+4]_crit                  Critical output current.
  93 curr[N+4]_crit_alarm            Output current critical alarm.
  94 curr[N+4]_max                   Maximum output current.
  95 curr[N+4]_max_alarm             Output current high alarm.
  96
  97 curr[N+P+5]_label               "iout1.P"
  98 curr[N+P+5]_input               VCORE phase P output current.
  99
 100 curr[2*N+5]_label               "iout3"
 101 curr[2*N+5]_input               VSA output current.
 102 curr[2*N+5]_highest             Historical maximum VSA output current.
 103 curr[2*N+5]_reset_history       Write any value to reset curr21_highest.
 104 curr[2*N+5]_crit                Critical output current.
 105 curr[2*N+5]_crit_alarm          Output current critical alarm.
 106 curr[2*N+5]_max                 Maximum output current.
 107 curr[2*N+5]_max_alarm           Output current high alarm.
 108
 109 power1_label                    "pin1"
 110 power1_input                    Input power, derived from duty cycle and output
 111                                 current.
 112 power1_alarm                    Input power alarm.
 113
 114 power2_label                    "pin2"
 115 power2_input                    Input power, derived from input current sensor.
 116
 117 power3_label                    "pout"
 118 power3_input                    Output power.
 119
 120 temp1_input                     VCORE temperature.
 121 temp1_crit                      Critical high temperature.
 122 temp1_crit_alarm                Chip temperature critical high alarm.
 123 temp1_max                       Maximum temperature.
 124 temp1_max_alarm                 Chip temperature high alarm.
 125
 126 temp2_input                     TSENSE_0 temperature
 127 temp3_input                     TSENSE_1 temperature
 128 temp4_input                     TSENSE_2 temperature
 129 temp5_input                     TSENSE_3 temperature
 130
 131 temp6_input                     VSA temperature.
 132 temp6_crit                      Critical high temperature.
 133 temp6_crit_alarm                Chip temperature critical high alarm.
 134 temp6_max                       Maximum temperature.
 135 temp6_max_alarm                 Chip temperature high alarm.
 136 =============================== ===============================================