1 ===========================
2 drm/i915 Intel GFX Driver
3 ===========================
5 The drm/i915 driver supports all (with the exception of some very early
6 models) integrated GFX chipsets with both Intel display and rendering
7 blocks. This excludes a set of SoC platforms with an SGX rendering unit,
8 those have basic support through the gma500 drm driver.
10 Core Driver Infrastructure
11 ==========================
13 This section covers core driver infrastructure used by both the display
14 and the GEM parts of the driver.
16 Runtime Power Management
17 ------------------------
19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
32 :doc: interrupt handling
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
38 :functions: intel_runtime_pm_disable_interrupts
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
41 :functions: intel_runtime_pm_enable_interrupts
43 Intel GVT-g Guest Support(vGPU)
44 -------------------------------
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
47 :doc: Intel GVT-g guest support
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
52 Intel GVT-g Host Support(vGPU device model)
53 -------------------------------------------
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
56 :doc: Intel GVT-g host support
58 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
64 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
65 :doc: Hardware workarounds
67 Display Hardware Handling
68 =========================
70 This section covers everything related to the display hardware including
71 the mode setting infrastructure, plane, sprite and cursor handling and
72 display, output probing and related topics.
74 Mode Setting Infrastructure
75 ---------------------------
77 The i915 driver is thus far the only DRM driver which doesn't use the
78 common DRM helper code to implement mode setting sequences. Thus it has
79 its own tailor-made infrastructure for executing a display configuration
85 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
86 :doc: frontbuffer tracking
88 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
91 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
94 Display FIFO Underrun Reporting
95 -------------------------------
97 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
98 :doc: fifo underrun handling
100 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
106 This section covers plane configuration and composition with the primary
107 plane, sprites, cursors and overlays. This includes the infrastructure
108 to do atomic vsync'ed updates of all this state and also tightly coupled
109 topics like watermark setup and computation, framebuffer compression and
115 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
116 :doc: atomic plane helpers
118 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
124 This section covers output probing and related infrastructure like the
125 hotplug interrupt storm detection and mitigation code. Note that the
126 i915 driver still uses most of the common DRM helper code for output
127 probing, so those sections fully apply.
132 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
135 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
138 High Definition Audio
139 ---------------------
141 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
142 :doc: High Definition Audio over HDMI and Display Port
144 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
147 .. kernel-doc:: include/drm/i915_component.h
150 Intel HDMI LPE Audio Support
151 ----------------------------
153 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
154 :doc: LPE Audio integration for HDMI or DP playback
156 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
159 Panel Self Refresh PSR (PSR/SRD)
160 --------------------------------
162 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
163 :doc: Panel Self Refresh (PSR/SRD)
165 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
168 Frame Buffer Compression (FBC)
169 ------------------------------
171 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
172 :doc: Frame Buffer Compression (FBC)
174 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
177 Display Refresh Rate Switching (DRRS)
178 -------------------------------------
180 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
181 :doc: Display Refresh Rate Switching (DRRS)
183 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
184 :functions: intel_dp_set_drrs_state
186 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
187 :functions: intel_edp_drrs_enable
189 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
190 :functions: intel_edp_drrs_disable
192 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
193 :functions: intel_edp_drrs_invalidate
195 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
196 :functions: intel_edp_drrs_flush
198 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
199 :functions: intel_dp_drrs_init
204 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
207 CSR firmware support for DMC
208 ----------------------------
210 .. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
211 :doc: csr support for dmc
213 .. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
216 Video BIOS Table (VBT)
217 ----------------------
219 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
220 :doc: Video BIOS Table (VBT)
222 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
225 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
231 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
234 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
240 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
243 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
246 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
249 Memory Management and Command Submission
250 ========================================
252 This sections covers all things related to the GEM implementation in the
258 An Intel GPU has multiple engines. There are several engine types.
260 - RCS engine is for rendering 3D and performing compute, this is named
261 `I915_EXEC_RENDER` in user space.
262 - BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
264 - VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
266 - VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
268 - The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
269 instead it is to be used by user space to specify a default rendering
270 engine (for 3D) that may or may not be the same as RCS.
272 The Intel GPU family is a family of integrated GPU's using Unified
273 Memory Access. For having the GPU "do work", user space will feed the
274 GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
275 or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
276 instruct the GPU to perform work (for example rendering) and that work
277 needs memory from which to read and memory to which to write. All memory
278 is encapsulated within GEM buffer objects (usually created with the ioctl
279 `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
280 to create will also list all GEM buffer objects that the batchbuffer reads
281 and/or writes. For implementation details of memory management see
282 `GEM BO Management Implementation Details`_.
284 The i915 driver allows user space to create a context via the ioctl
285 `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
286 integer. Such a context should be viewed by user-space as -loosely-
287 analogous to the idea of a CPU process of an operating system. The i915
288 driver guarantees that commands issued to a fixed context are to be
289 executed so that writes of a previously issued command are seen by
290 reads of following commands. Actions issued between different contexts
291 (even if from the same file descriptor) are NOT given that guarantee
292 and the only way to synchronize across contexts (even from the same
293 file descriptor) is through the use of fences. At least as far back as
294 Gen4, also have that a context carries with it a GPU HW context;
295 the HW context is essentially (most of atleast) the state of a GPU.
296 In addition to the ordering guarantees, the kernel will restore GPU
297 state via HW context when commands are issued to a context, this saves
298 user space the need to restore (most of atleast) the GPU state at the
299 start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
300 work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
301 to identify what context to use with the command.
303 The GPU has its own memory management and address space. The kernel
304 driver maintains the memory translation table for the GPU. For older
305 GPUs (i.e. those before Gen8), there is a single global such translation
306 table, a global Graphics Translation Table (GTT). For newer generation
307 GPUs each context has its own translation table, called Per-Process
308 Graphics Translation Table (PPGTT). Of important note, is that although
309 PPGTT is named per-process it is actually per context. When user space
310 submits a batchbuffer, the kernel walks the list of GEM buffer objects
311 used by the batchbuffer and guarantees that not only is the memory of
312 each such GEM buffer object resident but it is also present in the
313 (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
314 then it is given an address. Two consequences of this are: the kernel
315 needs to edit the batchbuffer submitted to write the correct value of
316 the GPU address when a GEM BO is assigned a GPU address and the kernel
317 might evict a different GEM BO from the (PP)GTT to make address room
318 for another GEM BO. Consequently, the ioctls submitting a batchbuffer
319 for execution also include a list of all locations within buffers that
320 refer to GPU-addresses so that the kernel can edit the buffer correctly.
321 This process is dubbed relocation.
323 GEM BO Management Implementation Details
324 ----------------------------------------
326 .. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
327 :doc: Virtual Memory Address
329 Buffer Object Eviction
330 ----------------------
332 This section documents the interface functions for evicting buffer
333 objects to make space available in the virtual gpu address spaces. Note
334 that this is mostly orthogonal to shrinking buffer objects caches, which
335 has the goal to make main memory (shared with the gpu through the
336 unified memory architecture) available.
338 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
341 Buffer Object Memory Shrinking
342 ------------------------------
344 This section documents the interface function for shrinking memory usage
345 of buffer object caches. Shrinking is used to make main memory
346 available. Note that this is mostly orthogonal to evicting buffer
347 objects, which has the goal to make space in gpu virtual address spaces.
349 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
355 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
356 :doc: batch buffer command parser
358 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
364 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
367 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
370 User Batchbuffer Execution
371 --------------------------
373 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
374 :doc: User command execution
376 Logical Rings, Logical Ring Contexts and Execlists
377 --------------------------------------------------
379 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
380 :doc: Logical Rings, Logical Ring Contexts and Execlists
385 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
386 :doc: Global GTT views
388 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
391 GTT Fences and Swizzling
392 ------------------------
394 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
397 Global GTT Fence Handling
398 ~~~~~~~~~~~~~~~~~~~~~~~~~
400 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
401 :doc: fence register handling
403 Hardware Tiling and Swizzling Details
404 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
406 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
407 :doc: tiling swizzling details
412 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
415 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
416 :doc: buffer object tiling
424 .. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
433 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
434 :doc: Firmware Layout
436 GuC-specific firmware loader
437 ----------------------------
439 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
442 GuC-based command submission
443 ----------------------------
445 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
446 :doc: GuC-based command submission
448 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
454 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
455 :doc: GuC Address Space
460 This sections covers all things related to the tracepoints implemented
463 i915_ppgtt_create and i915_ppgtt_release
464 ----------------------------------------
466 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
467 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
469 i915_context_create and i915_context_free
470 -----------------------------------------
472 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
473 :doc: i915_context_create and i915_context_free tracepoints
480 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
481 :doc: i915 Perf Overview
483 Comparison with Core Perf
484 -------------------------
485 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
486 :doc: i915 Perf History and Comparison with Core Perf
488 i915 Driver Entry Points
489 ------------------------
491 This section covers the entrypoints exported outside of i915_perf.c to
492 integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
494 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
495 :functions: i915_perf_init
496 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
497 :functions: i915_perf_fini
498 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
499 :functions: i915_perf_register
500 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
501 :functions: i915_perf_unregister
502 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
503 :functions: i915_perf_open_ioctl
504 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
505 :functions: i915_perf_release
506 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
507 :functions: i915_perf_add_config_ioctl
508 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
509 :functions: i915_perf_remove_config_ioctl
514 This section covers the stream-semantics-agnostic structures and functions
515 for representing an i915 perf stream FD and associated file operations.
517 .. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
518 :functions: i915_perf_stream
519 .. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
520 :functions: i915_perf_stream_ops
522 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
523 :functions: read_properties_unlocked
524 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
525 :functions: i915_perf_open_ioctl_locked
526 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
527 :functions: i915_perf_destroy_locked
528 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
529 :functions: i915_perf_read
530 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
531 :functions: i915_perf_ioctl
532 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
533 :functions: i915_perf_enable_locked
534 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
535 :functions: i915_perf_disable_locked
536 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
537 :functions: i915_perf_poll
538 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
539 :functions: i915_perf_poll_locked
541 i915 Perf Observation Architecture Stream
542 -----------------------------------------
544 .. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h
545 :functions: i915_oa_ops
547 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
548 :functions: i915_oa_stream_init
549 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
550 :functions: i915_oa_read
551 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
552 :functions: i915_oa_stream_enable
553 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
554 :functions: i915_oa_stream_disable
555 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
556 :functions: i915_oa_wait_unlocked
557 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
558 :functions: i915_oa_poll_wait
560 All i915 Perf Internals
561 -----------------------
563 This section simply includes all currently documented i915 perf internals, in
564 no particular order, but may include some more minor utilities or platform
565 specific details than found in the more high-level sections.
567 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
573 The drm/i915 driver codebase has some style rules in addition to (and, in some
574 cases, deviating from) the kernel coding style.
576 Register macro definition style
577 -------------------------------
579 The style guide for ``i915_reg.h``.
581 .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
582 :doc: The i915 register macro definition style guide