1 Buffer Sharing and Synchronization
2 ==================================
4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
6 for synchronizing asynchronous hardware access.
8 This is used, for example, by drm "prime" multi-GPU support, but is of
9 course not limited to GPU use cases.
11 The three main components of this are: (1) dma-buf, representing a
12 sg_table and exposed to userspace as a file descriptor to allow passing
13 between devices, (2) fence, which provides a mechanism to signal when
14 one device has finished access, and (3) reservation, which manages the
15 shared or exclusive fence(s) associated with the buffer.
20 This document serves as a guide to device-driver writers on what is the dma-buf
21 buffer sharing API, how to use it for exporting and using shared buffers.
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
24 either the 'exporter' of buffers, or the 'user' or 'importer' of buffers.
26 Say a driver A wants to use buffers created by driver B, then we call B as the
27 exporter, and A as buffer-user/importer.
31 - implements and manages operations in :c:type:`struct dma_buf_ops
32 <dma_buf_ops>` for the buffer,
33 - allows other users to share the buffer by using dma_buf sharing APIs,
34 - manages the details of buffer allocation, wrapped in a :c:type:`struct
36 - decides about the actual backing storage where this allocation happens,
37 - and takes care of any migration of scatterlist - for all (shared) users of
42 - is one of (many) sharing users of the buffer.
43 - doesn't need to worry about how the buffer is allocated, or where.
44 - and needs a mechanism to get access to the scatterlist that makes up this
45 buffer in memory, mapped into its own address space, so it can access the
46 same area of memory. This interface is provided by :c:type:`struct
47 dma_buf_attachment <dma_buf_attachment>`.
49 Any exporters or users of the dma-buf buffer sharing framework must have a
50 'select DMA_SHARED_BUFFER' in their respective Kconfigs.
52 Userspace Interface Notes
53 ~~~~~~~~~~~~~~~~~~~~~~~~~
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
56 and hence the generic interface exposed is very minimal. There's a few things to
59 - Since kernel 3.12 the dma-buf FD supports the llseek system call, but only
60 with offset=0 and whence=SEEK_END|SEEK_SET. SEEK_SET is supported to allow
61 the usual size discover pattern size = SEEK_END(0); SEEK_SET(0). Every other
62 llseek operation will report -EINVAL.
64 If llseek on dma-buf FDs isn't support the kernel will report -ESPIPE for all
65 cases. Userspace can use this to detect support for discovering the dma-buf
68 - In order to avoid fd leaks on exec, the FD_CLOEXEC flag must be set
69 on the file descriptor. This is not just a resource leak, but a
70 potential security hole. It could give the newly exec'd application
71 access to buffers, via the leaked fd, to which it should otherwise
72 not be permitted access.
74 The problem with doing this via a separate fcntl() call, versus doing it
75 atomically when the fd is created, is that this is inherently racy in a
76 multi-threaded app[3]. The issue is made worse when it is library code
77 opening/creating the file descriptor, as the application may not even be
80 To avoid this problem, userspace must have a way to request O_CLOEXEC
81 flag be set when the dma-buf fd is created. So any API provided by
82 the exporting driver to create a dmabuf fd must provide a way to let
83 userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
85 - Memory mapping the contents of the DMA buffer is also supported. See the
86 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
88 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
91 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
92 `DMA Buffer ioctls`_ below for details.
94 Basic Operation and Device DMA Access
95 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
97 .. kernel-doc:: drivers/dma-buf/dma-buf.c
98 :doc: dma buf device access
100 CPU Access to DMA Buffer Objects
101 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
103 .. kernel-doc:: drivers/dma-buf/dma-buf.c
106 Implicit Fence Poll Support
107 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
109 .. kernel-doc:: drivers/dma-buf/dma-buf.c
110 :doc: implicit fence polling
114 .. kernel-doc:: drivers/dma-buf/dma-buf-sysfs-stats.c
120 .. kernel-doc:: include/uapi/linux/dma-buf.h
122 Kernel Functions and Structures Reference
123 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
125 .. kernel-doc:: drivers/dma-buf/dma-buf.c
128 .. kernel-doc:: include/linux/dma-buf.h
131 Buffer Mapping Helpers
132 ~~~~~~~~~~~~~~~~~~~~~~
134 .. kernel-doc:: include/linux/dma-buf-map.h
137 .. kernel-doc:: include/linux/dma-buf-map.h
143 .. kernel-doc:: drivers/dma-buf/dma-resv.c
144 :doc: Reservation Object Overview
146 .. kernel-doc:: drivers/dma-buf/dma-resv.c
149 .. kernel-doc:: include/linux/dma-resv.h
155 .. kernel-doc:: drivers/dma-buf/dma-fence.c
156 :doc: DMA fences overview
158 DMA Fence Cross-Driver Contract
159 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
161 .. kernel-doc:: drivers/dma-buf/dma-fence.c
162 :doc: fence cross-driver contract
164 DMA Fence Signalling Annotations
165 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
167 .. kernel-doc:: drivers/dma-buf/dma-fence.c
168 :doc: fence signalling annotation
170 DMA Fences Functions Reference
171 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
173 .. kernel-doc:: drivers/dma-buf/dma-fence.c
176 .. kernel-doc:: include/linux/dma-fence.h
179 Seqno Hardware Fences
180 ~~~~~~~~~~~~~~~~~~~~~
182 .. kernel-doc:: include/linux/seqno-fence.h
188 .. kernel-doc:: drivers/dma-buf/dma-fence-array.c
191 .. kernel-doc:: include/linux/dma-fence-array.h
197 .. kernel-doc:: drivers/dma-buf/dma-fence-chain.c
200 .. kernel-doc:: include/linux/dma-fence-chain.h
203 DMA Fence uABI/Sync File
204 ~~~~~~~~~~~~~~~~~~~~~~~~
206 .. kernel-doc:: drivers/dma-buf/sync_file.c
209 .. kernel-doc:: include/linux/sync_file.h
212 Indefinite DMA Fences
213 ~~~~~~~~~~~~~~~~~~~~~
215 At various times struct dma_fence with an indefinite time until dma_fence_wait()
216 finishes have been proposed. Examples include:
218 * Future fences, used in HWC1 to signal when a buffer isn't used by the display
219 any longer, and created with the screen update that makes the buffer visible.
220 The time this fence completes is entirely under userspace's control.
222 * Proxy fences, proposed to handle &drm_syncobj for which the fence has not yet
223 been set. Used to asynchronously delay command submission.
225 * Userspace fences or gpu futexes, fine-grained locking within a command buffer
226 that userspace uses for synchronization across engines or with the CPU, which
227 are then imported as a DMA fence for integration into existing winsys
230 * Long-running compute command buffers, while still using traditional end of
231 batch DMA fences for memory management instead of context preemption DMA
232 fences which get reattached when the compute job is rescheduled.
234 Common to all these schemes is that userspace controls the dependencies of these
235 fences and controls when they fire. Mixing indefinite fences with normal
236 in-kernel DMA fences does not work, even when a fallback timeout is included to
237 protect against malicious userspace:
239 * Only the kernel knows about all DMA fence dependencies, userspace is not aware
240 of dependencies injected due to memory management or scheduler decisions.
242 * Only userspace knows about all dependencies in indefinite fences and when
243 exactly they will complete, the kernel has no visibility.
245 Furthermore the kernel has to be able to hold up userspace command submission
246 for memory management needs, which means we must support indefinite fences being
247 dependent upon DMA fences. If the kernel also support indefinite fences in the
248 kernel like a DMA fence, like any of the above proposal would, there is the
249 potential for deadlocks.
251 .. kernel-render:: DOT
252 :alt: Indefinite Fencing Dependency Cycle
253 :caption: Indefinite Fencing Dependency Cycle
255 digraph "Fencing Cycle" {
256 node [shape=box bgcolor=grey style=filled]
257 kernel [label="Kernel DMA Fences"]
258 userspace [label="userspace controlled fences"]
259 kernel -> userspace [label="memory management"]
260 userspace -> kernel [label="Future fence, fence proxy, ..."]
262 { rank=same; kernel userspace }
265 This means that the kernel might accidentally create deadlocks
266 through memory management dependencies which userspace is unaware of, which
267 randomly hangs workloads until the timeout kicks in. Workloads, which from
268 userspace's perspective, do not contain a deadlock. In such a mixed fencing
269 architecture there is no single entity with knowledge of all dependencies.
270 Thefore preventing such deadlocks from within the kernel is not possible.
272 The only solution to avoid dependencies loops is by not allowing indefinite
273 fences in the kernel. This means:
275 * No future fences, proxy fences or userspace fences imported as DMA fences,
276 with or without a timeout.
278 * No DMA fences that signal end of batchbuffer for command submission where
279 userspace is allowed to use userspace fencing or long running compute
280 workloads. This also means no implicit fencing for shared buffers in these
283 Recoverable Hardware Page Faults Implications
284 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
286 Modern hardware supports recoverable page faults, which has a lot of
287 implications for DMA fences.
289 First, a pending page fault obviously holds up the work that's running on the
290 accelerator and a memory allocation is usually required to resolve the fault.
291 But memory allocations are not allowed to gate completion of DMA fences, which
292 means any workload using recoverable page faults cannot use DMA fences for
293 synchronization. Synchronization fences controlled by userspace must be used
296 On GPUs this poses a problem, because current desktop compositor protocols on
297 Linux rely on DMA fences, which means without an entirely new userspace stack
298 built on top of userspace fences, they cannot benefit from recoverable page
299 faults. Specifically this means implicit synchronization will not be possible.
300 The exception is when page faults are only used as migration hints and never to
301 on-demand fill a memory request. For now this means recoverable page
302 faults on GPUs are limited to pure compute workloads.
304 Furthermore GPUs usually have shared resources between the 3D rendering and
305 compute side, like compute units or command submission engines. If both a 3D
306 job with a DMA fence and a compute workload using recoverable page faults are
307 pending they could deadlock:
309 - The 3D workload might need to wait for the compute job to finish and release
310 hardware resources first.
312 - The compute workload might be stuck in a page fault, because the memory
313 allocation is waiting for the DMA fence of the 3D workload to complete.
315 There are a few options to prevent this problem, one of which drivers need to
318 - Compute workloads can always be preempted, even when a page fault is pending
319 and not yet repaired. Not all hardware supports this.
321 - DMA fence workloads and workloads which need page fault handling have
322 independent hardware resources to guarantee forward progress. This could be
323 achieved through e.g. through dedicated engines and minimal compute unit
324 reservations for DMA fence workloads.
326 - The reservation approach could be further refined by only reserving the
327 hardware resources for DMA fence workloads when they are in-flight. This must
328 cover the time from when the DMA fence is visible to other threads up to
329 moment when fence is completed through dma_fence_signal().
331 - As a last resort, if the hardware provides no useful reservation mechanics,
332 all workloads must be flushed from the GPU when switching between jobs
333 requiring DMA fences or jobs requiring page fault handling: This means all DMA
334 fences must complete before a compute job with page fault handling can be
335 inserted into the scheduler queue. And vice versa, before a DMA fence can be
336 made visible anywhere in the system, all compute workloads must be preempted
337 to guarantee all pending GPU page faults are flushed.
339 - Only a fairly theoretical option would be to untangle these dependencies when
340 allocating memory to repair hardware page faults, either through separate
341 memory blocks or runtime tracking of the full dependency graph of all DMA
342 fences. This results very wide impact on the kernel, since resolving the page
343 on the CPU side can itself involve a page fault. It is much more feasible and
344 robust to limit the impact of handling hardware page faults to the specific
347 Note that workloads that run on independent hardware like copy engines or other
348 GPUs do not have any impact. This allows us to keep using DMA fences internally
349 in the kernel even for resolving hardware page faults, e.g. by using copy
350 engines to clear or copy memory needed to resolve the page fault.
352 In some ways this page fault problem is a special case of the `Infinite DMA
353 Fences` discussions: Infinite fences from compute workloads are allowed to
354 depend on DMA fences, but not the other way around. And not even the page fault
355 problem is new, because some other CPU thread in userspace might
356 hit a page fault which holds up a userspace fence - supporting page faults on
357 GPUs doesn't anything fundamentally new.