1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive Watchdog for JH7100 and JH7110 SoC
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
17 output(WDOGINT) will rise when counter is 0. The counter will reload
18 the timeout value. And then, if counter decreases to 0 again and WDOGINT
19 isn't cleared, the watchdog will reset the system unless the watchdog
23 - $ref: watchdog.yaml#
39 - description: APB clock
40 - description: Core clock
49 - description: APB reset
50 - description: Core reset
59 unevaluatedProperties: false
64 compatible = "starfive,jh7100-wdt";
65 reg = <0x12480000 0x10000>;
68 clock-names = "apb", "core";