Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
   8
   9 maintainers:
  10   - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
  11
  12 properties:
  13   $nodename:
  14     pattern: "^(watchdog|timer)@[0-9a-f]+$"
  15
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - qcom,kpss-wdt-ipq4019
  21               - qcom,apss-wdt-ipq5018
  22               - qcom,apss-wdt-ipq5332
  23               - qcom,apss-wdt-ipq9574
  24               - qcom,apss-wdt-msm8226
  25               - qcom,apss-wdt-msm8974
  26               - qcom,apss-wdt-msm8994
  27               - qcom,apss-wdt-qcm2290
  28               - qcom,apss-wdt-qcs404
  29               - qcom,apss-wdt-sa8775p
  30               - qcom,apss-wdt-sc7180
  31               - qcom,apss-wdt-sc7280
  32               - qcom,apss-wdt-sc8180x
  33               - qcom,apss-wdt-sc8280xp
  34               - qcom,apss-wdt-sdm845
  35               - qcom,apss-wdt-sdx55
  36               - qcom,apss-wdt-sdx65
  37               - qcom,apss-wdt-sm6115
  38               - qcom,apss-wdt-sm6350
  39               - qcom,apss-wdt-sm8150
  40               - qcom,apss-wdt-sm8250
  41           - const: qcom,kpss-wdt
  42       - const: qcom,kpss-wdt
  43         deprecated: true
  44       - items:
  45           - const: qcom,scss-timer
  46           - const: qcom,msm-timer
  47       - items:
  48           - enum:
  49               - qcom,kpss-wdt-apq8064
  50               - qcom,kpss-wdt-ipq8064
  51               - qcom,kpss-wdt-mdm9615
  52               - qcom,kpss-wdt-msm8960
  53           - const: qcom,kpss-timer
  54           - const: qcom,msm-timer
  55
  56   reg:
  57     maxItems: 1
  58
  59   clocks:
  60     maxItems: 1
  61
  62   clock-names:
  63     items:
  64       - const: sleep
  65
  66   clock-frequency:
  67     description:
  68       The frequency of the general purpose timer in Hz.
  69
  70   cpu-offset:
  71     $ref: /schemas/types.yaml#/definitions/uint32
  72     description:
  73       Per-CPU offset used when the timer is accessed without the CPU remapping
  74       facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
  75
  76   interrupts:
  77     minItems: 1
  78     maxItems: 5
  79
  80 required:
  81   - compatible
  82   - reg
  83   - clocks
  84
  85 allOf:
  86   - $ref: watchdog.yaml#
  87
  88   - if:
  89       properties:
  90         compatible:
  91           contains:
  92             const: qcom,kpss-wdt
  93     then:
  94       properties:
  95         clock-frequency: false
  96         cpu-offset: false
  97         interrupts:
  98           minItems: 1
  99           items:
 100             - description: Bark
 101             - description: Bite
 102
 103     else:
 104       properties:
 105         interrupts:
 106           minItems: 3
 107           items:
 108             - description: Debug
 109             - description: First general purpose timer
 110             - description: Second general purpose timer
 111             - description: First watchdog
 112             - description: Second watchdog
 113       required:
 114         - clock-frequency
 115
 116 unevaluatedProperties: false
 117
 118 examples:
 119   - |
 120     #include <dt-bindings/interrupt-controller/arm-gic.h>
 121
 122     watchdog@17c10000 {
 123         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
 124         reg = <0x17c10000 0x1000>;
 125         clocks = <&sleep_clk>;
 126         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 127         timeout-sec = <10>;
 128     };
 129
 130   - |
 131     #include <dt-bindings/interrupt-controller/arm-gic.h>
 132
 133     watchdog@200a000 {
 134         compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
 135         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 136                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 137                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 138                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
 139                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 140         reg = <0x0200a000 0x100>;
 141         clock-frequency = <25000000>;
 142         clocks = <&sleep_clk>;
 143         clock-names = "sleep";
 144         cpu-offset = <0x80000>;
 145     };