1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence watchdog timer controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The cadence watchdog timer is used to detect and recover from
14 system malfunctions. This watchdog contains 24 bit counter and
15 a programmable reset period. The timeout period varies from 1 ms
16 to 30 seconds while using a 100Mhz clock.
19 - $ref: watchdog.yaml#
38 If this property exists, then a reset is done when watchdog
47 unevaluatedProperties: false
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 compatible = "cdns,wdt-r1p2";
55 reg = <0xf8005000 0x1000>;
57 interrupt-parent = <&intc>;
58 interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;