1 # SPDX-License-Identifier: GPL-2.0
4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
10 - Roger Quadros <rogerq@kernel.org>
28 PM domain provider node and an args specifier containing
29 the USB device id value. See,
30 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
34 description: Clock phandles to usb2_refclk and lpm_clk
45 If present, it restricts the controller to USB2.0 mode of
46 operation. Must be present if USB3 PHY is not available
52 Should be present if USB VBUS line is connected to the
53 VBUS pin of the SoC via a 1/3 voltage divider.
59 assigned-clock-parents:
81 additionalProperties: false
85 #include <dt-bindings/soc/ti,sci_pm_domain.h>
86 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 compatible = "ti,j721e-usb";
94 reg = <0x00 0x4104000 0x00 0x100>;
95 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
96 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
97 clock-names = "ref", "lpm";
98 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
99 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
100 #address-cells = <2>;
104 compatible = "cdns,usb3";
105 reg = <0x00 0x6000000 0x00 0x10000>,
106 <0x00 0x6010000 0x00 0x10000>,
107 <0x00 0x6020000 0x00 0x10000>;
108 reg-names = "otg", "xhci", "dev";
109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
110 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
111 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
112 interrupt-names = "host",
115 maximum-speed = "super-speed";