Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: TI wrapper module for the Cadence USBSS-DRD controller
   8
   9 maintainers:
  10   - Roger Quadros <rogerq@kernel.org>
  11
  12 properties:
  13   compatible:
  14     oneOf:
  15       - const: ti,j721e-usb
  16       - const: ti,am64-usb
  17       - items:
  18           - const: ti,j721e-usb
  19           - const: ti,am64-usb
  20
  21   reg:
  22     maxItems: 1
  23
  24   ranges: true
  25
  26   power-domains:
  27     description:
  28       PM domain provider node and an args specifier containing
  29       the USB device id value. See,
  30       Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
  31     maxItems: 1
  32
  33   clocks:
  34     description: Clock phandles to usb2_refclk and lpm_clk
  35     minItems: 2
  36     maxItems: 2
  37
  38   clock-names:
  39     items:
  40       - const: ref
  41       - const: lpm
  42
  43   ti,usb2-only:
  44     description:
  45       If present, it restricts the controller to USB2.0 mode of
  46       operation. Must be present if USB3 PHY is not available
  47       for USB.
  48     type: boolean
  49
  50   ti,vbus-divider:
  51     description:
  52       Should be present if USB VBUS line is connected to the
  53       VBUS pin of the SoC via a 1/3 voltage divider.
  54     type: boolean
  55
  56   '#address-cells':
  57     const: 2
  58
  59   '#size-cells':
  60     const: 2
  61
  62   dma-coherent: true
  63
  64 patternProperties:
  65   "^usb@":
  66     type: object
  67
  68 required:
  69   - compatible
  70   - reg
  71   - power-domains
  72   - clocks
  73   - clock-names
  74
  75 additionalProperties: false
  76
  77 examples:
  78   - |
  79     #include <dt-bindings/soc/ti,sci_pm_domain.h>
  80     #include <dt-bindings/interrupt-controller/arm-gic.h>
  81
  82     bus {
  83         #address-cells = <2>;
  84         #size-cells = <2>;
  85
  86         cdns_usb@4104000 {
  87             compatible = "ti,j721e-usb";
  88             reg = <0x00 0x4104000 0x00 0x100>;
  89             power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
  90             clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
  91             clock-names = "ref", "lpm";
  92             assigned-clocks = <&k3_clks 288 15>;        /* USB2_REFCLK */
  93             assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
  94             #address-cells = <2>;
  95             #size-cells = <2>;
  96
  97             usb@6000000 {
  98                   compatible = "cdns,usb3";
  99                   reg = <0x00 0x6000000 0x00 0x10000>,
 100                         <0x00 0x6010000 0x00 0x10000>,
 101                         <0x00 0x6020000 0x00 0x10000>;
 102                   reg-names = "otg", "xhci", "dev";
 103                   interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,        /* irq.0 */
 104                                <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,       /* irq.6 */
 105                                <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;       /* otgirq.0 */
 106                   interrupt-names = "host",
 107                                     "peripheral",
 108                                     "otg";
 109                   maximum-speed = "super-speed";
 110                   dr_mode = "otg";
 111             };
 112         };
 113     };