1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
30 - nvidia,tegra114-ehci
31 - nvidia,tegra124-ehci
32 - nvidia,tegra210-ehci
33 - const: nvidia,tegra30-ehci
49 - const: fsl,imx27-usb
54 - const: fsl,imx7ulp-usb
55 - const: fsl,imx6ul-usb
60 - const: fsl,imx7d-usb
61 - const: fsl,imx27-usb
66 - const: fsl,imx6ul-usb
67 - const: fsl,imx27-usb
69 - const: xlnx,zynq-usb-2.20a
70 - const: chipidea,usb2
74 - const: nuvoton,npcm750-udc
110 interrupt threshold control register control, the setting should be
111 aligned with ITC bits at register USBCMD.
112 $ref: /schemas/types.yaml#/definitions/uint32
116 it is vendor dependent, the required value should be aligned with
117 AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is
118 used to change AHB burst configuration, check the chipidea spec for
119 meaning of each value. If this property is not existed, it will use
121 $ref: /schemas/types.yaml#/definitions/uint32
127 it is vendor dependent, the tx burst size in dword (4 bytes), This
128 register represents the maximum length of a the burst in 32-bit
129 words while moving data from system memory to the USB bus, the value
130 of this property will only take effect if property "ahb-burst-config"
131 is set to 0, if this property is missing the reset default of the
132 hardware implementation will be used.
133 $ref: /schemas/types.yaml#/definitions/uint32
139 it is vendor dependent, the rx burst size in dword (4 bytes), This
140 register represents the maximum length of a the burst in 32-bit words
141 while moving data from the USB bus to system memory, the value of
142 this property will only take effect if property "ahb-burst-config"
143 is set to 0, if this property is missing the reset default of the
144 hardware implementation will be used.
145 $ref: /schemas/types.yaml#/definitions/uint32
151 Phandles to external connector devices. First phandle should point
152 to external connector, which provide "USB" cable events, the second
153 should point to external connector device, which provide "USB-HOST"
154 cable events. If one of the external connector devices is not
155 required, empty <0> phandle should be specified.
156 $ref: /schemas/types.yaml#/definitions/phandle-array
159 - description: vbus extcon
160 - description: id extcon
162 phy-clkgate-delay-us:
164 The delay time (us) between putting the PHY into low power mode and
165 gating the PHY clock.
167 non-zero-ttctrl-ttha:
169 After setting this property, the value of register ttctrl.ttha
170 will be 0x7f; if not, the value will be 0x0, this is the default
171 value. It needs to be very carefully for setting this property, it
172 is recommended that consult with your IC engineer before setting
173 this value. On the most of chipidea platforms, the "usage_tt" flag
174 at RTL is 0, so this property only affects siTD.
176 If this property is not set, the max packet size is 1023 bytes, and
177 if the total of packet size for previous transactions are more than
178 256 bytes, it can't accept any transactions within this frame. The
179 use case is single transaction, but higher frame rate.
181 If this property is set, the max packet size is 188 bytes, it can
182 handle more transactions than above case, it can accept transactions
183 until it considers the left room size within frame is less than 188
184 bytes, software needs to make sure it does not send more than 90%
185 maximum_periodic_data_per_frame. The use case is multiple
186 transactions, but less frame rate.
191 The mux control for toggling host/device output of this controller.
192 It's expected that a mux state of 0 indicates device mode and a mux
193 state of 1 indicates host mode.
200 description: A phandle to the OPP table containing the performance states.
201 $ref: /schemas/types.yaml#/definitions/phandle
205 Names for optional pin modes in "default", "host", "device".
206 In case of HSIC-mode, "idle" and "active" pin modes are mandatory.
207 In this case, the "idle" state needs to pull down the data and
208 strobe pin and the "active" state needs to pull up the strobe pin.
235 Phandler of TCSR node with two argument that indicate register
236 offset, and phy index
237 $ref: /schemas/types.yaml#/definitions/phandle-array
239 - description: phandle to TCSR node
240 - description: register offset
241 - description: phy index
244 description: reference to the VBUS regulator.
248 Phandler of non-core register device, with one argument that
249 indicate usb controller index
250 $ref: /schemas/types.yaml#/definitions/phandle-array
253 - description: phandle to usbmisc node
254 - description: index of usb controller
257 description: phandle for the anatop node.
258 $ref: /schemas/types.yaml#/definitions/phandle
260 disable-over-current:
262 description: disable over current detect
264 over-current-active-low:
266 description: over current signal polarity is active low
268 over-current-active-high:
271 Over current signal polarity is active high. It's recommended to
272 specify the over current polarity.
276 description: power signal polarity is active high
278 external-vbus-divider:
280 description: enables off-chip resistor divider for Vbus
282 samsung,picophy-pre-emp-curr-control:
284 HS Transmitter Pre-Emphasis Current Control. This signal controls
285 the amount of current sourced to the USB_OTG*_DP and USB_OTG*_DN
286 pins after a J-to-K or K-to-J transition. The range is from 0x0 to
287 0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0
288 bits of USBNC_n_PHY_CFG1.
289 $ref: /schemas/types.yaml#/definitions/uint32
293 samsung,picophy-dc-vol-level-adjust:
295 HS DC Voltage Level Adjustment. Adjust the high-speed transmitter DC
296 level voltage. The range is from 0x0 to 0xf, the default value is
297 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
298 $ref: /schemas/types.yaml#/definitions/uint32
302 fsl,picophy-rise-fall-time-adjust:
304 HS Transmitter Rise/Fall Time Adjustment. Adjust the rise/fall times
305 of the high-speed transmitter waveform. It has no unit. The rise/fall
306 time will be increased or decreased by a certain percentage relative
307 to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%)
308 Details can refer to TXRISETUNE0 bit of USBNC_n_PHY_CFG1.
309 $ref: /schemas/types.yaml#/definitions/uint32
315 description: phandle for the PHY device. Use "phys" instead.
316 $ref: /schemas/types.yaml#/definitions/phandle
320 description: phandle of usb phy that connects to the port. Use "phys" instead.
321 $ref: /schemas/types.yaml#/definitions/phandle
325 description: phandle of usb phy that connects to the port. Use "phys" instead.
326 $ref: /schemas/types.yaml#/definitions/phandle
329 nvidia,needs-double-reset:
330 description: Indicates double reset or not.
336 Any connector to the data bus of this controller should be modelled
337 using the OF graph bindings specified, if the "usb-role-switch"
339 $ref: /schemas/graph.yaml#/properties/port
346 additionalProperties: false
349 description: The phy child node for Qcom chips.
351 $ref: /schemas/phy/qcom,usb-hs-phy.yaml
354 port: [ usb-role-switch ]
355 mux-controls: [ mux-control-names ]
363 - $ref: usb-hcd.yaml#
364 - $ref: usb-drd.yaml#
397 - nuvoton,npcm750-udc
400 - nvidia,tegra114-udc
401 - nvidia,tegra124-udc
403 - xlnx,zynq-usb-2.20a
407 disable-over-current: false
408 over-current-active-low: false
409 over-current-active-high: false
410 power-active-high: false
411 external-vbus-divider: false
412 samsung,picophy-pre-emp-curr-control: false
413 samsung,picophy-dc-vol-level-adjust: false
415 unevaluatedProperties: false
419 #include <dt-bindings/interrupt-controller/arm-gic.h>
420 #include <dt-bindings/clock/berlin2.h>
423 compatible = "chipidea,usb2";
424 reg = <0xf7ed0000 0x10000>;
425 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&chip CLKID_USB0>;
428 phy-names = "usb-phy";
429 vbus-supply = <®_usb0_vbus>;
430 itc-setting = <0x4>; /* 4 micro-frames */
431 /* Incremental burst of unspecified length */
432 ahb-burst-config = <0x0>;
433 tx-burst-size-dword = <0x10>; /* 64 bytes */
434 rx-burst-size-dword = <0x10>;
435 extcon = <0>, <&usb_id>;
436 phy-clkgate-delay-us = <400>;
437 mux-controls = <&usb_switch>;
438 mux-control-names = "usb_switch";
443 #include <dt-bindings/interrupt-controller/arm-gic.h>
444 #include <dt-bindings/clock/imx6qdl-clock.h>
447 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
448 reg = <0x02184400 0x200>;
449 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6QDL_CLK_USBOH3>;
451 fsl,usbphy = <&usbphynop1>;
452 fsl,usbmisc = <&usbmisc 2>;
455 ahb-burst-config = <0x0>;
456 tx-burst-size-dword = <0x10>;
457 rx-burst-size-dword = <0x10>;
458 pinctrl-names = "idle", "active";
459 pinctrl-0 = <&pinctrl_usbh2_idle>;
460 pinctrl-1 = <&pinctrl_usbh2_active>;
461 #address-cells = <1>;
465 compatible = "usb424,9730";