1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI J721e UFS Host Controller Glue Driver
10 - Vignesh Raghavendra <vigneshr@ti.com>
19 description: address of TI UFS glue registers
23 description: phandle to the M-PHY clock
31 assigned-clock-parents:
52 Cadence UFS controller node must be the child node.
53 unevaluatedProperties: false
55 additionalProperties: false
59 #include <dt-bindings/interrupt-controller/irq.h>
60 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 compatible = "ti,j721e-ufs";
68 reg = <0x0 0x4e80000 0x0 0x100>;
69 power-domains = <&k3_pds 277>;
70 clocks = <&k3_clks 277 1>;
71 assigned-clocks = <&k3_clks 277 1>;
72 assigned-clock-parents = <&k3_clks 277 4>;
74 ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
79 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
80 reg = <0x0 0x4000 0x0 0x10000>;
81 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
82 freq-table-hz = <19200000 19200000>;
83 power-domains = <&k3_pds 277>;
84 clocks = <&k3_clks 277 1>;
85 assigned-clocks = <&k3_clks 277 1>;
86 assigned-clock-parents = <&k3_clks 277 4>;
87 clock-names = "core_clk";