Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung SoC series UFS host controller Device Tree Bindings
   8
   9 maintainers:
  10   - Alim Akhtar <alim.akhtar@samsung.com>
  11
  12 description: |
  13   Each Samsung UFS host controller instance should have its own node.
  14   This binding define Samsung specific binding other then what is used
  15   in the common ufshcd bindings
  16   [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
  17
  18 properties:
  19
  20   compatible:
  21     enum:
  22       - samsung,exynos7-ufs
  23
  24   reg:
  25     items:
  26       - description: HCI register
  27       - description: vendor specific register
  28       - description: unipro register
  29       - description: UFS protector register
  30
  31   reg-names:
  32     items:
  33       - const: hci
  34       - const: vs_hci
  35       - const: unipro
  36       - const: ufsp
  37
  38   clocks:
  39     items:
  40       - description: ufs link core clock
  41       - description: unipro main clock
  42
  43   clock-names:
  44     items:
  45       - const: core_clk
  46       - const: sclk_unipro_main
  47
  48   interrupts:
  49     maxItems: 1
  50
  51   phys:
  52     maxItems: 1
  53
  54   phy-names:
  55     const: ufs-phy
  56
  57 required:
  58   - compatible
  59   - reg
  60   - interrupts
  61   - phys
  62   - phy-names
  63   - clocks
  64   - clock-names
  65
  66 additionalProperties: false
  67
  68 examples:
  69   - |
  70     #include <dt-bindings/interrupt-controller/arm-gic.h>
  71     #include <dt-bindings/clock/exynos7-clk.h>
  72
  73     ufs: ufs@15570000 {
  74        compatible = "samsung,exynos7-ufs";
  75        reg = <0x15570000 0x100>,
  76              <0x15570100 0x100>,
  77              <0x15571000 0x200>,
  78              <0x15572000 0x300>;
  79        reg-names = "hci", "vs_hci", "unipro", "ufsp";
  80        interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  81        clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
  82                 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
  83        clock-names = "core_clk", "sclk_unipro_main";
  84        pinctrl-names = "default";
  85        pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
  86        phys = <&ufs_phy>;
  87        phy-names = "ufs-phy";
  88     };
  89 ...