1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
37 - const: jedec,ufs-2.0
87 GPIO connected to the RESET pin of the UFS memory device.
94 - $ref: ufs-common.yaml
102 - qcom,sc8280xp-ufshc
114 - const: bus_aggr_clk
116 - const: core_clk_unipro
118 - const: tx_lane0_sync_clk
119 - const: rx_lane0_sync_clk
120 - const: rx_lane1_sync_clk
141 - const: bus_aggr_clk
143 - const: core_clk_unipro
145 - const: tx_lane0_sync_clk
146 - const: rx_lane0_sync_clk
147 - const: rx_lane1_sync_clk
148 - const: ice_core_clk
166 - const: core_clk_src
169 - const: bus_aggr_clk
171 - const: core_clk_unipro_src
172 - const: core_clk_unipro
173 - const: core_clk_ice
175 - const: tx_lane0_sync_clk
176 - const: rx_lane0_sync_clk
181 # TODO: define clock bindings for qcom,msm8994-ufshc
183 unevaluatedProperties: false
187 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
188 #include <dt-bindings/clock/qcom,rpmh.h>
189 #include <dt-bindings/gpio/gpio.h>
190 #include <dt-bindings/interconnect/qcom,sm8450.h>
191 #include <dt-bindings/interrupt-controller/arm-gic.h>
194 #address-cells = <2>;
198 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
200 reg = <0 0x01d84000 0 0x3000>;
201 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
202 phys = <&ufs_mem_phy_lanes>;
203 phy-names = "ufsphy";
204 lanes-per-direction = <2>;
206 resets = <&gcc GCC_UFS_PHY_BCR>;
208 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
210 vcc-supply = <&vreg_l7b_2p5>;
211 vcc-max-microamp = <1100000>;
212 vccq-supply = <&vreg_l9b_1p2>;
213 vccq-max-microamp = <1200000>;
215 power-domains = <&gcc UFS_PHY_GDSC>;
216 iommus = <&apps_smmu 0xe0 0x0>;
217 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
218 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
219 interconnect-names = "ufs-ddr", "cpu-ufs";
221 clock-names = "core_clk",
229 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
230 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
231 <&gcc GCC_UFS_PHY_AHB_CLK>,
232 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
233 <&rpmhcc RPMH_CXO_CLK>,
234 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
235 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
236 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
237 freq-table-hz = <75000000 300000000>,
240 <75000000 300000000>,
241 <75000000 300000000>,