Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Universal Flash Storage (UFS) Controller
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11   - Andy Gross <agross@kernel.org>
  12
  13 # Select only our matches, not all jedec,ufs-2.0
  14 select:
  15   properties:
  16     compatible:
  17       contains:
  18         const: qcom,ufshc
  19   required:
  20     - compatible
  21
  22 properties:
  23   compatible:
  24     items:
  25       - enum:
  26           - qcom,msm8994-ufshc
  27           - qcom,msm8996-ufshc
  28           - qcom,msm8998-ufshc
  29           - qcom,sdm845-ufshc
  30           - qcom,sm6350-ufshc
  31           - qcom,sm8150-ufshc
  32           - qcom,sm8250-ufshc
  33           - qcom,sm8350-ufshc
  34           - qcom,sm8450-ufshc
  35       - const: qcom,ufshc
  36       - const: jedec,ufs-2.0
  37
  38   clocks:
  39     minItems: 8
  40     maxItems: 11
  41
  42   clock-names:
  43     minItems: 8
  44     maxItems: 11
  45
  46   interconnects:
  47     minItems: 2
  48     maxItems: 2
  49
  50   interconnect-names:
  51     items:
  52       - const: ufs-ddr
  53       - const: cpu-ufs
  54
  55   iommus:
  56     minItems: 1
  57     maxItems: 2
  58
  59   phys:
  60     maxItems: 1
  61
  62   phy-names:
  63     items:
  64       - const: ufsphy
  65
  66   power-domains:
  67     maxItems: 1
  68
  69   reg:
  70     minItems: 1
  71     maxItems: 2
  72
  73   resets:
  74     maxItems: 1
  75
  76   '#reset-cells':
  77     const: 1
  78
  79   reset-names:
  80     items:
  81       - const: rst
  82
  83   reset-gpios:
  84     maxItems: 1
  85     description:
  86       GPIO connected to the RESET pin of the UFS memory device.
  87
  88 required:
  89   - compatible
  90   - reg
  91
  92 allOf:
  93   - $ref: ufs-common.yaml
  94
  95   - if:
  96       properties:
  97         compatible:
  98           contains:
  99             enum:
 100               - qcom,msm8998-ufshc
 101               - qcom,sm8250-ufshc
 102               - qcom,sm8350-ufshc
 103               - qcom,sm8450-ufshc
 104     then:
 105       properties:
 106         clocks:
 107           minItems: 8
 108           maxItems: 8
 109         clock-names:
 110           items:
 111             - const: core_clk
 112             - const: bus_aggr_clk
 113             - const: iface_clk
 114             - const: core_clk_unipro
 115             - const: ref_clk
 116             - const: tx_lane0_sync_clk
 117             - const: rx_lane0_sync_clk
 118             - const: rx_lane1_sync_clk
 119         reg:
 120           minItems: 1
 121           maxItems: 1
 122
 123   - if:
 124       properties:
 125         compatible:
 126           contains:
 127             enum:
 128               - qcom,sdm845-ufshc
 129               - qcom,sm6350-ufshc
 130               - qcom,sm8150-ufshc
 131     then:
 132       properties:
 133         clocks:
 134           minItems: 9
 135           maxItems: 9
 136         clock-names:
 137           items:
 138             - const: core_clk
 139             - const: bus_aggr_clk
 140             - const: iface_clk
 141             - const: core_clk_unipro
 142             - const: ref_clk
 143             - const: tx_lane0_sync_clk
 144             - const: rx_lane0_sync_clk
 145             - const: rx_lane1_sync_clk
 146             - const: ice_core_clk
 147         reg:
 148           minItems: 2
 149           maxItems: 2
 150
 151   - if:
 152       properties:
 153         compatible:
 154           contains:
 155             enum:
 156               - qcom,msm8996-ufshc
 157     then:
 158       properties:
 159         clocks:
 160           minItems: 11
 161           maxItems: 11
 162         clock-names:
 163           items:
 164             - const: core_clk_src
 165             - const: core_clk
 166             - const: bus_clk
 167             - const: bus_aggr_clk
 168             - const: iface_clk
 169             - const: core_clk_unipro_src
 170             - const: core_clk_unipro
 171             - const: core_clk_ice
 172             - const: ref_clk
 173             - const: tx_lane0_sync_clk
 174             - const: rx_lane0_sync_clk
 175         reg:
 176           minItems: 1
 177           maxItems: 1
 178
 179     # TODO: define clock bindings for qcom,msm8994-ufshc
 180
 181 unevaluatedProperties: false
 182
 183 examples:
 184   - |
 185     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 186     #include <dt-bindings/clock/qcom,rpmh.h>
 187     #include <dt-bindings/gpio/gpio.h>
 188     #include <dt-bindings/interconnect/qcom,sm8450.h>
 189     #include <dt-bindings/interrupt-controller/arm-gic.h>
 190
 191     soc {
 192         #address-cells = <2>;
 193         #size-cells = <2>;
 194
 195         ufs@1d84000 {
 196             compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
 197                          "jedec,ufs-2.0";
 198             reg = <0 0x01d84000 0 0x3000>;
 199             interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 200             phys = <&ufs_mem_phy_lanes>;
 201             phy-names = "ufsphy";
 202             lanes-per-direction = <2>;
 203             #reset-cells = <1>;
 204             resets = <&gcc GCC_UFS_PHY_BCR>;
 205             reset-names = "rst";
 206             reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
 207
 208             vcc-supply = <&vreg_l7b_2p5>;
 209             vcc-max-microamp = <1100000>;
 210             vccq-supply = <&vreg_l9b_1p2>;
 211             vccq-max-microamp = <1200000>;
 212
 213             power-domains = <&gcc UFS_PHY_GDSC>;
 214             iommus = <&apps_smmu 0xe0 0x0>;
 215             interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
 216                             <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
 217             interconnect-names = "ufs-ddr", "cpu-ufs";
 218
 219             clock-names = "core_clk",
 220                           "bus_aggr_clk",
 221                           "iface_clk",
 222                           "core_clk_unipro",
 223                           "ref_clk",
 224                           "tx_lane0_sync_clk",
 225                           "rx_lane0_sync_clk",
 226                           "rx_lane1_sync_clk";
 227             clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
 228                      <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 229                      <&gcc GCC_UFS_PHY_AHB_CLK>,
 230                      <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 231                      <&rpmhcc RPMH_CXO_CLK>,
 232                      <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 233                      <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 234                      <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
 235             freq-table-hz = <75000000 300000000>,
 236                             <0 0>,
 237                             <0 0>,
 238                             <75000000 300000000>,
 239                             <75000000 300000000>,
 240                             <0 0>,
 241                             <0 0>,
 242                             <0 0>;
 243         };
 244     };