Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Universal Flash Storage (UFS) Controller
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11   - Andy Gross <agross@kernel.org>
  12
  13 # Select only our matches, not all jedec,ufs-2.0
  14 select:
  15   properties:
  16     compatible:
  17       contains:
  18         const: qcom,ufshc
  19   required:
  20     - compatible
  21
  22 properties:
  23   compatible:
  24     items:
  25       - enum:
  26           - qcom,msm8994-ufshc
  27           - qcom,msm8996-ufshc
  28           - qcom,msm8998-ufshc
  29           - qcom,sa8775p-ufshc
  30           - qcom,sc8280xp-ufshc
  31           - qcom,sdm845-ufshc
  32           - qcom,sm6115-ufshc
  33           - qcom,sm6350-ufshc
  34           - qcom,sm8150-ufshc
  35           - qcom,sm8250-ufshc
  36           - qcom,sm8350-ufshc
  37           - qcom,sm8450-ufshc
  38           - qcom,sm8550-ufshc
  39           - qcom,sm8650-ufshc
  40       - const: qcom,ufshc
  41       - const: jedec,ufs-2.0
  42
  43   clocks:
  44     minItems: 8
  45     maxItems: 11
  46
  47   clock-names:
  48     minItems: 8
  49     maxItems: 11
  50
  51   dma-coherent: true
  52
  53   interconnects:
  54     minItems: 2
  55     maxItems: 2
  56
  57   interconnect-names:
  58     items:
  59       - const: ufs-ddr
  60       - const: cpu-ufs
  61
  62   iommus:
  63     minItems: 1
  64     maxItems: 2
  65
  66   phys:
  67     maxItems: 1
  68
  69   phy-names:
  70     items:
  71       - const: ufsphy
  72
  73   power-domains:
  74     maxItems: 1
  75
  76   qcom,ice:
  77     $ref: /schemas/types.yaml#/definitions/phandle
  78     description: phandle to the Inline Crypto Engine node
  79
  80   reg:
  81     minItems: 1
  82     maxItems: 2
  83
  84   reg-names:
  85     items:
  86       - const: std
  87       - const: ice
  88
  89   required-opps:
  90     maxItems: 1
  91
  92   resets:
  93     maxItems: 1
  94
  95   '#reset-cells':
  96     const: 1
  97
  98   reset-names:
  99     items:
 100       - const: rst
 101
 102   reset-gpios:
 103     maxItems: 1
 104     description:
 105       GPIO connected to the RESET pin of the UFS memory device.
 106
 107 required:
 108   - compatible
 109   - reg
 110
 111 allOf:
 112   - $ref: ufs-common.yaml
 113
 114   - if:
 115       properties:
 116         compatible:
 117           contains:
 118             enum:
 119               - qcom,msm8998-ufshc
 120               - qcom,sa8775p-ufshc
 121               - qcom,sc8280xp-ufshc
 122               - qcom,sm8250-ufshc
 123               - qcom,sm8350-ufshc
 124               - qcom,sm8450-ufshc
 125               - qcom,sm8550-ufshc
 126               - qcom,sm8650-ufshc
 127     then:
 128       properties:
 129         clocks:
 130           minItems: 8
 131           maxItems: 8
 132         clock-names:
 133           items:
 134             - const: core_clk
 135             - const: bus_aggr_clk
 136             - const: iface_clk
 137             - const: core_clk_unipro
 138             - const: ref_clk
 139             - const: tx_lane0_sync_clk
 140             - const: rx_lane0_sync_clk
 141             - const: rx_lane1_sync_clk
 142         reg:
 143           minItems: 1
 144           maxItems: 1
 145         reg-names:
 146           maxItems: 1
 147
 148   - if:
 149       properties:
 150         compatible:
 151           contains:
 152             enum:
 153               - qcom,sdm845-ufshc
 154               - qcom,sm6350-ufshc
 155               - qcom,sm8150-ufshc
 156     then:
 157       properties:
 158         clocks:
 159           minItems: 9
 160           maxItems: 9
 161         clock-names:
 162           items:
 163             - const: core_clk
 164             - const: bus_aggr_clk
 165             - const: iface_clk
 166             - const: core_clk_unipro
 167             - const: ref_clk
 168             - const: tx_lane0_sync_clk
 169             - const: rx_lane0_sync_clk
 170             - const: rx_lane1_sync_clk
 171             - const: ice_core_clk
 172         reg:
 173           minItems: 2
 174           maxItems: 2
 175         reg-names:
 176           minItems: 2
 177       required:
 178         - reg-names
 179
 180   - if:
 181       properties:
 182         compatible:
 183           contains:
 184             enum:
 185               - qcom,msm8996-ufshc
 186     then:
 187       properties:
 188         clocks:
 189           minItems: 11
 190           maxItems: 11
 191         clock-names:
 192           items:
 193             - const: core_clk_src
 194             - const: core_clk
 195             - const: bus_clk
 196             - const: bus_aggr_clk
 197             - const: iface_clk
 198             - const: core_clk_unipro_src
 199             - const: core_clk_unipro
 200             - const: core_clk_ice
 201             - const: ref_clk
 202             - const: tx_lane0_sync_clk
 203             - const: rx_lane0_sync_clk
 204         reg:
 205           minItems: 1
 206           maxItems: 1
 207         reg-names:
 208           maxItems: 1
 209
 210   - if:
 211       properties:
 212         compatible:
 213           contains:
 214             enum:
 215               - qcom,sm6115-ufshc
 216     then:
 217       properties:
 218         clocks:
 219           minItems: 8
 220           maxItems: 8
 221         clock-names:
 222           items:
 223             - const: core_clk
 224             - const: bus_aggr_clk
 225             - const: iface_clk
 226             - const: core_clk_unipro
 227             - const: ref_clk
 228             - const: tx_lane0_sync_clk
 229             - const: rx_lane0_sync_clk
 230             - const: ice_core_clk
 231         reg:
 232           minItems: 2
 233           maxItems: 2
 234         reg-names:
 235           minItems: 2
 236       required:
 237         - reg-names
 238
 239     # TODO: define clock bindings for qcom,msm8994-ufshc
 240
 241   - if:
 242       required:
 243         - qcom,ice
 244     then:
 245       properties:
 246         reg:
 247           maxItems: 1
 248         clocks:
 249           minItems: 8
 250           maxItems: 8
 251     else:
 252       properties:
 253         reg:
 254           minItems: 1
 255           maxItems: 2
 256         clocks:
 257           minItems: 8
 258           maxItems: 11
 259
 260 unevaluatedProperties: false
 261
 262 examples:
 263   - |
 264     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 265     #include <dt-bindings/clock/qcom,rpmh.h>
 266     #include <dt-bindings/gpio/gpio.h>
 267     #include <dt-bindings/interconnect/qcom,sm8450.h>
 268     #include <dt-bindings/interrupt-controller/arm-gic.h>
 269
 270     soc {
 271         #address-cells = <2>;
 272         #size-cells = <2>;
 273
 274         ufs@1d84000 {
 275             compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
 276                          "jedec,ufs-2.0";
 277             reg = <0 0x01d84000 0 0x3000>;
 278             interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 279             phys = <&ufs_mem_phy_lanes>;
 280             phy-names = "ufsphy";
 281             lanes-per-direction = <2>;
 282             #reset-cells = <1>;
 283             resets = <&gcc GCC_UFS_PHY_BCR>;
 284             reset-names = "rst";
 285             reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
 286
 287             vcc-supply = <&vreg_l7b_2p5>;
 288             vcc-max-microamp = <1100000>;
 289             vccq-supply = <&vreg_l9b_1p2>;
 290             vccq-max-microamp = <1200000>;
 291
 292             power-domains = <&gcc UFS_PHY_GDSC>;
 293             iommus = <&apps_smmu 0xe0 0x0>;
 294             interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
 295                             <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
 296             interconnect-names = "ufs-ddr", "cpu-ufs";
 297
 298             clock-names = "core_clk",
 299                           "bus_aggr_clk",
 300                           "iface_clk",
 301                           "core_clk_unipro",
 302                           "ref_clk",
 303                           "tx_lane0_sync_clk",
 304                           "rx_lane0_sync_clk",
 305                           "rx_lane1_sync_clk";
 306             clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
 307                      <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 308                      <&gcc GCC_UFS_PHY_AHB_CLK>,
 309                      <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 310                      <&rpmhcc RPMH_CXO_CLK>,
 311                      <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 312                      <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 313                      <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
 314             freq-table-hz = <75000000 300000000>,
 315                             <0 0>,
 316                             <0 0>,
 317                             <75000000 300000000>,
 318                             <75000000 300000000>,
 319                             <0 0>,
 320                             <0 0>,
 321                             <0 0>;
 322             qcom,ice = <&ice>;
 323         };
 324     };