1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Core Local Interruptor
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
28 - sifive,fu540-c000-clint
29 - starfive,jh7100-clint
31 - const: sifive,clint0
33 - const: sifive,clint0
36 description: For the QEMU virt machine only
39 Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
40 Supported compatible strings are -
41 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
42 onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
43 CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
44 "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
46 Please refer to sifive-blocks-ip-versioning.txt for details
55 additionalProperties: false
65 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
66 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
67 <&cpu2intc 3>, <&cpu2intc 7>,
68 <&cpu3intc 3>, <&cpu3intc 7>,
69 <&cpu4intc 3>, <&cpu4intc 7>;
70 reg = <0x2000000 0x10000>;