1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
18 one CPU local timer instantiated in MCT for every CPU in the system.
24 - samsung,exynos4210-mct
25 - samsung,exynos4412-mct
28 - samsung,exynos3250-mct
29 - samsung,exynos5250-mct
30 - samsung,exynos5260-mct
31 - samsung,exynos5420-mct
32 - samsung,exynos5433-mct
33 - samsung,exynos850-mct
35 - const: samsung,exynos4210-mct
50 Interrupts should be put in specific order. This is, the local timer
51 interrupts should be specified after the four global timer interrupts
53 0: Global Timer Interrupt 0
54 1: Global Timer Interrupt 1
55 2: Global Timer Interrupt 2
56 3: Global Timer Interrupt 3
57 4: Local Timer Interrupt 0
58 5: Local Timer Interrupt 1
61 i: Local Timer Interrupt n
62 For MCT block that uses a per-processor interrupt for local timers, such
63 as ones compatible with "samsung,exynos4412-mct", only one local timer
64 interrupt might be specified, meaning that all local timers use the same
65 per processor interrupt.
66 minItems: 5 # 4 Global + 1 local
67 maxItems: 20 # 4 Global + 16 local
81 const: samsung,exynos3250-mct
92 const: samsung,exynos5250-mct
104 - samsung,exynos5260-mct
105 - samsung,exynos5420-mct
106 - samsung,exynos5433-mct
107 - samsung,exynos850-mct
126 additionalProperties: false
130 // In this example, the IP contains two local timers, using separate
131 // interrupts, so two local timer interrupts have been specified,
132 // in addition to four global timer interrupts.
133 #include <dt-bindings/clock/exynos4.h>
134 #include <dt-bindings/interrupt-controller/arm-gic.h>
137 compatible = "samsung,exynos4210-mct";
138 reg = <0x10050000 0x800>;
139 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
140 clock-names = "fin_pll", "mct";
142 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
151 // In this example, the timer interrupts are connected to two separate
152 // interrupt controllers. Hence, an interrupts-extended is needed.
153 #include <dt-bindings/clock/exynos4.h>
154 #include <dt-bindings/interrupt-controller/arm-gic.h>
157 compatible = "samsung,exynos4210-mct";
158 reg = <0x101C0000 0x800>;
159 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
160 clock-names = "fin_pll", "mct";
162 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
163 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
166 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
167 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
171 // In this example, the IP contains four local timers, but using
172 // a per-processor interrupt to handle them. Only one first local
173 // interrupt is specified.
174 #include <dt-bindings/clock/exynos4.h>
175 #include <dt-bindings/interrupt-controller/arm-gic.h>
178 compatible = "samsung,exynos4412-mct";
179 reg = <0x10050000 0x800>;
180 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
181 clock-names = "fin_pll", "mct";
183 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
191 // In this example, the IP contains four local timers, but using
192 // a per-processor interrupt to handle them. All the local timer
193 // interrupts are specified.
194 #include <dt-bindings/clock/exynos4.h>
195 #include <dt-bindings/interrupt-controller/arm-gic.h>
198 compatible = "samsung,exynos4412-mct";
199 reg = <0x10050000 0x800>;
200 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
201 clock-names = "fin_pll", "mct";
203 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;