Documentation/devicetree/bindings/timer/riscv,timer.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V timer
   8
   9 maintainers:
  10   - Anup Patel <anup@brainfault.org>
  11
  12 description: |+
  13   RISC-V platforms always have a RISC-V timer device for the supervisor-mode
  14   based on the time CSR defined by the RISC-V privileged specification. The
  15   timer interrupts of this device are configured using the RISC-V SBI Time
  16   extension or the RISC-V Sstc extension.
  17
  18   The clock frequency of RISC-V timer device is specified via the
  19   "timebase-frequency" DT property of "/cpus" DT node which is described
  20   in Documentation/devicetree/bindings/riscv/cpus.yaml
  21
  22 properties:
  23   compatible:
  24     enum:
  25       - riscv,timer
  26
  27   interrupts-extended:
  28     minItems: 1
  29     maxItems: 4096   # Should be enough?
  30
  31   riscv,timer-cannot-wake-cpu:
  32     type: boolean
  33     description:
  34       If present, the timer interrupt cannot wake up the CPU from one or
  35       more suspend/idle states.
  36
  37 additionalProperties: false
  38
  39 required:
  40   - compatible
  41   - interrupts-extended
  42
  43 examples:
  44   - |
  45     timer {
  46       compatible = "riscv,timer";
  47       interrupts-extended = <&cpu1intc 5>,
  48                             <&cpu2intc 5>,
  49                             <&cpu3intc 5>,
  50                             <&cpu4intc 5>;
  51     };
  52 ...