Documentation/devicetree/bindings/timer/renesas,ostm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas OS Timer (OSTM)
   8
   9 maintainers:
  10   - Chris Brandt <chris.brandt@renesas.com>
  11   - Geert Uytterhoeven <geert+renesas@glider.be>
  12
  13 description:
  14   The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
  15   can operate in either interval count down timer or free-running compare match
  16   mode.
  17
  18   Channels are independent from each other.
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - renesas,r7s72100-ostm  # RZ/A1H
  25           - renesas,r7s9210-ostm   # RZ/A2M
  26           - renesas,r9a07g043-ostm # RZ/G2UL
  27           - renesas,r9a07g044-ostm # RZ/G2{L,LC}
  28           - renesas,r9a07g054-ostm # RZ/V2L
  29       - const: renesas,ostm        # Generic
  30
  31   reg:
  32     maxItems: 1
  33
  34   interrupts:
  35     maxItems: 1
  36
  37   clocks:
  38     maxItems: 1
  39
  40   power-domains:
  41     maxItems: 1
  42
  43   resets:
  44     maxItems: 1
  45
  46 required:
  47   - compatible
  48   - reg
  49   - interrupts
  50   - clocks
  51   - power-domains
  52
  53 if:
  54   properties:
  55     compatible:
  56       contains:
  57         enum:
  58           - renesas,r9a07g043-ostm
  59           - renesas,r9a07g044-ostm
  60           - renesas,r9a07g054-ostm
  61 then:
  62   required:
  63     - resets
  64
  65 additionalProperties: false
  66
  67 examples:
  68   - |
  69     #include <dt-bindings/clock/r7s72100-clock.h>
  70     #include <dt-bindings/interrupt-controller/arm-gic.h>
  71     ostm0: timer@fcfec000 {
  72             compatible = "renesas,r7s72100-ostm", "renesas,ostm";
  73             reg = <0xfcfec000 0x30>;
  74             interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
  75             clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
  76             power-domains = <&cpg_clocks>;
  77     };