Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra timer
   8
   9 maintainers:
  10   - Stephen Warren <swarren@nvidia.com>
  11
  12 allOf:
  13   - if:
  14       properties:
  15         compatible:
  16           contains:
  17             const: nvidia,tegra210-timer
  18     then:
  19       properties:
  20         interrupts:
  21           # Either a single combined interrupt or up to 14 individual interrupts
  22           minItems: 1
  23           maxItems: 14
  24           description: >
  25             A list of 14 interrupts; one per each timer channels 0 through 13
  26
  27   - if:
  28       properties:
  29         compatible:
  30           oneOf:
  31             - items:
  32                 - enum:
  33                     - nvidia,tegra114-timer
  34                     - nvidia,tegra124-timer
  35                     - nvidia,tegra132-timer
  36                 - const: nvidia,tegra30-timer
  37             - items:
  38                 - const: nvidia,tegra30-timer
  39                 - const: nvidia,tegra20-timer
  40     then:
  41       properties:
  42         interrupts:
  43           # Either a single combined interrupt or up to 6 individual interrupts
  44           minItems: 1
  45           maxItems: 6
  46           description: >
  47             A list of 6 interrupts; one per each of timer channels 1 through 5,
  48             and one for the shared interrupt for the remaining channels.
  49
  50   - if:
  51       properties:
  52         compatible:
  53           const: nvidia,tegra20-timer
  54     then:
  55       properties:
  56         interrupts:
  57           # Either a single combined interrupt or up to 4 individual interrupts
  58           minItems: 1
  59           maxItems: 4
  60           description: |
  61             A list of 4 interrupts; one per timer channel.
  62
  63 properties:
  64   compatible:
  65     oneOf:
  66       - const: nvidia,tegra210-timer
  67         description: >
  68           The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
  69           timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
  70           from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
  71           (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
  72           or watchdog interrupts.
  73       - items:
  74           - enum:
  75               - nvidia,tegra114-timer
  76               - nvidia,tegra124-timer
  77               - nvidia,tegra132-timer
  78           - const: nvidia,tegra30-timer
  79       - items:
  80           - const: nvidia,tegra30-timer
  81           - const: nvidia,tegra20-timer
  82         description: >
  83           The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
  84           running counter, and 5 watchdog modules. The first two channels may also
  85           trigger a legacy watchdog reset.
  86       - const: nvidia,tegra20-timer
  87         description: >
  88           The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
  89           running counter. The first two channels may also trigger a watchdog reset.
  90
  91   reg:
  92     maxItems: 1
  93
  94   interrupts: true
  95
  96   clocks:
  97     maxItems: 1
  98
  99   clock-names:
 100     items:
 101       - const: timer
 102
 103
 104 required:
 105   - compatible
 106   - reg
 107   - interrupts
 108   - clocks
 109
 110 additionalProperties: false
 111
 112 examples:
 113   - |
 114     #include <dt-bindings/interrupt-controller/irq.h>
 115     timer@60005000 {
 116         compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 117         reg = <0x60005000 0x400>;
 118         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 119                      <0 1 IRQ_TYPE_LEVEL_HIGH>,
 120                      <0 41 IRQ_TYPE_LEVEL_HIGH>,
 121                      <0 42 IRQ_TYPE_LEVEL_HIGH>,
 122                      <0 121 IRQ_TYPE_LEVEL_HIGH>,
 123                      <0 122 IRQ_TYPE_LEVEL_HIGH>;
 124         clocks = <&tegra_car 214>;
 125     };
 126   - |
 127     #include <dt-bindings/clock/tegra210-car.h>
 128     #include <dt-bindings/interrupt-controller/arm-gic.h>
 129     #include <dt-bindings/interrupt-controller/irq.h>
 130
 131     timer@60005000 {
 132         compatible = "nvidia,tegra210-timer";
 133         reg = <0x60005000 0x400>;
 134         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 135                      <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 136                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 137                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 138                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 139                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 140                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 141                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 142                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 143                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 144                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 145                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 146                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 147                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 148         clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 149         clock-names = "timer";
 150     };