1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
26 - arm,cortex-a15-timer
39 - description: secure timer irq
40 - description: non-secure timer irq
41 - description: virtual timer irq
42 - description: hypervisor timer irq
43 - description: hypervisor virtual timer irq
62 description: The frequency of the main counter, in Hz. Should be present
63 only where necessary to work around broken firmware which does not configure
64 CNTFRQ on all CPUs to a uniform correct value. Use of this property is
65 strongly discouraged; fix your firmware unless absolutely impossible.
69 description: If present, the timer is powered through an always-on power
70 domain, therefore it never loses context.
72 allwinner,erratum-unknown1:
74 description: Indicates the presence of an erratum found in Allwinner SoCs,
75 where reading certain values from the counter is unreliable. This also
76 affects writes to the tval register, due to the implicit counter read.
80 description: Indicates the presence of QorIQ erratum A-008585, which says
81 that reading the counter is unreliable unless the same value is returned
82 by back-to-back reads. This also affects writes to the tval register, due
83 to the implicit counter read.
85 hisilicon,erratum-161010101:
87 description: Indicates the presence of Hisilicon erratum 161010101, which
88 says that reading the counters is unreliable in some cases, and reads may
89 return a value 32 beyond the correct value. This also affects writes to
90 the tval registers, due to the implicit counter read.
92 arm,cpu-registers-not-fw-configured:
94 description: Firmware does not initialize any of the generic timer CPU
95 registers, which contain their architecturally-defined reset values. Only
96 supported for 32-bit systems which follow the ARMv7 architected reset
99 arm,no-tick-in-suspend:
101 description: The main counter does not tick when the system is in
102 low-power system suspend on some SoCs. This behavior does not match the
103 Architecture Reference Manual's specification that the system counter "must
104 be implemented in an always-on power domain."
109 additionalProperties: false
115 - interrupts-extended
120 compatible = "arm,cortex-a15-timer",
122 interrupts = <1 13 0xf08>,
126 clock-frequency = <100000000>;