1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
25 - const: arm,cortex-a15-timer
26 - const: arm,armv7-timer
32 - const: arm,armv8-timer
33 - const: arm,armv7-timer
38 - description: secure timer irq
39 - description: non-secure timer irq
40 - description: virtual timer irq
41 - description: hypervisor timer irq
42 - description: hypervisor virtual timer irq
61 description: The frequency of the main counter, in Hz. Should be present
62 only where necessary to work around broken firmware which does not configure
63 CNTFRQ on all CPUs to a uniform correct value. Use of this property is
64 strongly discouraged; fix your firmware unless absolutely impossible.
68 description: If present, the timer is powered through an always-on power
69 domain, therefore it never loses context.
71 allwinner,erratum-unknown1:
73 description: Indicates the presence of an erratum found in Allwinner SoCs,
74 where reading certain values from the counter is unreliable. This also
75 affects writes to the tval register, due to the implicit counter read.
79 description: Indicates the presence of QorIQ erratum A-008585, which says
80 that reading the counter is unreliable unless the same value is returned
81 by back-to-back reads. This also affects writes to the tval register, due
82 to the implicit counter read.
84 hisilicon,erratum-161010101:
86 description: Indicates the presence of Hisilicon erratum 161010101, which
87 says that reading the counters is unreliable in some cases, and reads may
88 return a value 32 beyond the correct value. This also affects writes to
89 the tval registers, due to the implicit counter read.
91 arm,cpu-registers-not-fw-configured:
93 description: Firmware does not initialize any of the generic timer CPU
94 registers, which contain their architecturally-defined reset values. Only
95 supported for 32-bit systems which follow the ARMv7 architected reset
98 arm,no-tick-in-suspend:
100 description: The main counter does not tick when the system is in
101 low-power system suspend on some SoCs. This behavior does not match the
102 Architecture Reference Manual's specification that the system counter "must
103 be implemented in an always-on power domain."
108 additionalProperties: false
114 - interrupts-extended
119 compatible = "arm,cortex-a15-timer",
121 interrupts = <1 13 0xf08>,
125 clock-frequency = <100000000>;