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[releases.git] / Documentation / devicetree / bindings / thermal / rzg2l-thermal.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/thermal/rzg2l-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas RZ/G2L Thermal Sensor Unit
8
9 description:
10   On RZ/G2L SoCs, the thermal sensor unit (TSU) measures the
11   temperature(Tj) inside the LSI.
12
13 maintainers:
14   - Biju Das <biju.das.jz@bp.renesas.com>
15
16 properties:
17   compatible:
18     items:
19       - enum:
20           - renesas,r9a07g043-tsu # RZ/G2UL
21           - renesas,r9a07g044-tsu # RZ/G2{L,LC}
22           - renesas,r9a07g054-tsu # RZ/V2L
23       - const: renesas,rzg2l-tsu
24
25   reg:
26     maxItems: 1
27
28   clocks:
29     maxItems: 1
30
31   power-domains:
32     maxItems: 1
33
34   resets:
35     maxItems: 1
36
37   "#thermal-sensor-cells":
38     const: 1
39
40 required:
41   - compatible
42   - reg
43   - clocks
44   - power-domains
45   - resets
46   - "#thermal-sensor-cells"
47
48 additionalProperties: false
49
50 examples:
51   - |
52     #include <dt-bindings/clock/r9a07g044-cpg.h>
53
54     tsu: thermal@10059400 {
55             compatible = "renesas,r9a07g044-tsu",
56                          "renesas,rzg2l-tsu";
57             reg = <0x10059400 0x400>;
58             clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
59             resets = <&cpg R9A07G044_TSU_PRESETN>;
60             power-domains = <&cpg>;
61             #thermal-sensor-cells = <1>;
62     };
63
64     thermal-zones {
65             cpu-thermal {
66                     polling-delay-passive = <250>;
67                     polling-delay = <1000>;
68                     thermal-sensors = <&tsu 0>;
69
70                     trips {
71                             sensor_crit: sensor-crit {
72                                     temperature = <125000>;
73                                     hysteresis = <1000>;
74                                     type = "critical";
75                             };
76                     };
77             };
78     };