1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021 Linaro Ltd.
5 $id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Limits Management Hardware(LMh)
11 - Thara Gopinath <thara.gopinath@linaro.org>
14 Limits Management Hardware(LMh) is a hardware infrastructure on some
15 Qualcomm SoCs that can enforce temperature and current limits as
16 programmed by software for certain IPs like CPU.
25 - description: core registers
33 interrupt-controller: true
37 phandle of the first cpu in the LMh cluster
38 $ref: /schemas/types.yaml#/definitions/phandle
40 qcom,lmh-temp-arm-millicelsius:
42 An integer expressing temperature threshold at which the LMh thermal
45 qcom,lmh-temp-low-millicelsius:
47 An integer expressing temperature threshold at which the state machine
48 will attempt to remove frequency throttling.
50 qcom,lmh-temp-high-millicelsius:
52 An integer expressing temperature threshold at which the state machine
53 will attempt to throttle the frequency.
60 - interrupt-controller
62 - qcom,lmh-temp-arm-millicelsius
63 - qcom,lmh-temp-low-millicelsius
64 - qcom,lmh-temp-high-millicelsius
66 additionalProperties: false
70 #include <dt-bindings/interrupt-controller/arm-gic.h>
73 compatible = "qcom,sdm845-lmh";
74 reg = <0x17d70800 0x400>;
75 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
77 qcom,lmh-temp-arm-millicelsius = <65000>;
78 qcom,lmh-temp-low-millicelsius = <94500>;
79 qcom,lmh-temp-high-millicelsius = <95000>;
81 #interrupt-cells = <1>;