1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
13 Simple IO memory regions to be managed by the genalloc API.
15 Each child of the sram node specifies a region of reserved memory. Each
16 child node should use a 'reg' property to specify a specific range of
19 Following the generic-names recommended practice, node names should
20 reflect the purpose of the node. Unit address (@<address>) should be
25 pattern: "^sram(@.*)?"
31 - amlogic,meson-gxbb-sram
33 - atmel,sama5d2-securam
34 - nvidia,tegra186-sysram
35 - nvidia,tegra194-sysram
36 - nvidia,tegra234-sysram
38 - rockchip,rk3288-pmu-sram
46 A list of phandle and clock specifier pair that controls the single
58 Should translate from local addresses within the sram to bus addresses.
62 The flag indicating, that SRAM memory region has not to be remapped
63 as write combining. WC is used by default.
67 "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
70 Each child of the sram node specifies a region of reserved memory.
74 Should contain a vendor specific string in the form
75 <vendor>,[<device>-]<usage>
78 - allwinner,sun4i-a10-sram-a3-a4
79 - allwinner,sun4i-a10-sram-c1
80 - allwinner,sun4i-a10-sram-d
81 - allwinner,sun9i-a80-smp-sram
82 - allwinner,sun50i-a64-sram-c
83 - amlogic,meson8-ao-arc-sram
84 - amlogic,meson8b-ao-arc-sram
85 - amlogic,meson8-smp-sram
86 - amlogic,meson8b-smp-sram
87 - amlogic,meson-gxbb-scp-shmem
88 - amlogic,meson-axg-scp-shmem
93 - rockchip,rk3066-smp-sram
94 - samsung,exynos4210-sysram
95 - samsung,exynos4210-sysram-ns
96 - socionext,milbeaut-smp-sram
100 IO mem address range, relative to the SRAM range.
105 Indicates that the particular reserved SRAM area is addressable
106 and in use by another device or devices.
111 Indicates that the reserved SRAM area may be accessed outside
112 of the kernel, e.g. by bootloader or userspace.
117 Same as 'pool' above but with the additional constraint that code
118 will be run from the region and that the memory is maintained as
119 read-only, executable during code execution. NOTE: This region must
120 be page aligned on start and end in order to properly allow
121 manipulation of the page attributes.
126 The name for the reserved partition, if omitted, the label is taken
127 from the node name excluding the unit address.
132 additionalProperties: false
145 - rockchip,rk3288-pmu-sram
152 additionalProperties: false
157 compatible = "mmio-sram";
158 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
160 #address-cells = <1>;
162 ranges = <0 0x5c000000 0x40000>;
169 reg = <0x1000 0x1000>;
173 exported-sram@20000 {
174 reg = <0x20000 0x20000>;
180 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
181 // of the secondary cores. Once the core gets powered up it executes the
182 // code that is residing at some specific location of the SYSRAM.
184 // Therefore reserved section sub-nodes have to be added to the mmio-sram
185 // declaration. These nodes are of two types depending upon secure or
186 // non-secure execution environment.
188 compatible = "mmio-sram";
189 reg = <0x02020000 0x54000>;
190 #address-cells = <1>;
192 ranges = <0 0x02020000 0x54000>;
195 compatible = "samsung,exynos4210-sysram";
200 compatible = "samsung,exynos4210-sysram-ns";
201 reg = <0x53000 0x1000>;
206 // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
207 // Once the core gets powered up it executes the code that is residing at a
208 // specific location.
210 // Therefore a reserved section sub-node has to be added to the mmio-sram
213 compatible = "mmio-sram";
214 reg = <0xd9000000 0x20000>;
215 #address-cells = <1>;
217 ranges = <0 0xd9000000 0x20000>;
220 compatible = "amlogic,meson8b-smp-sram";
227 compatible = "mmio-sram";
228 reg = <0xe63c0000 0x1000>;
229 #address-cells = <1>;
231 ranges = <0 0xe63c0000 0x1000>;
234 compatible = "renesas,smp-sram";
241 compatible = "mmio-sram";
242 reg = <0x10080000 0x10000>;
243 #address-cells = <1>;
248 compatible = "rockchip,rk3066-smp-sram";
249 reg = <0x10080000 0x50>;
254 // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
255 // resume from maskrom(the 1st level loader). This is a common use of
256 // the "pmu-sram" because it keeps power even in low power states
259 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
260 reg = <0xff720000 0x1000>;
264 // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
265 // primary core (cpu0). Once the core gets powered up it checks if a magic
266 // value is set at a specific location. If it is then the BROM will jump
267 // to the software entry address, instead of executing a standard boot.
269 // Also there are no "secure-only" properties. The implementation should
270 // check if this SRAM is usable first.
272 // 256 KiB secure SRAM at 0x20000
273 compatible = "mmio-sram";
274 reg = <0x00020000 0x40000>;
275 #address-cells = <1>;
277 ranges = <0 0x00020000 0x40000>;
280 // This is checked by BROM to determine if
281 // cpu0 should jump to SMP entry vector
282 compatible = "allwinner,sun9i-a80-smp-sram";
289 compatible = "mmio-sram";
291 #address-cells = <1>;
293 ranges = <0 0x0 0x10000>;
296 compatible = "socionext,milbeaut-smp-sram";