1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Spreadtrum ADI controller
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 ADI is the abbreviation of Anolog-Digital interface, which is used to access
17 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
18 framework for its hardware implementation is alike to SPI bus and its timing
19 is compatile to SPI timing.
21 ADI controller has 50 channels including 2 software read/write channels and
22 48 hardware channels to access analog chip. For 2 software read/write channels,
23 users should set ADI registers to access analog chip. For hardware channels,
24 we can configure them to allow other hardware components to use it independently,
25 which means we can just link one analog chip address to one hardware channel,
26 then users can access the mapped analog chip address by this hardware channel
27 triggered by hardware components instead of ADI software channels.
29 Thus we introduce one property named "sprd,hw-channels" to configure hardware
30 channels, the first value specifies the hardware channel id which is used to
31 transfer data triggered by hardware automatically, and the second value specifies
32 the analog chip address where user want to access by hardware components.
34 Since we have multi-subsystems will use unique ADI to access analog chip, when
35 one system is reading/writing data by ADI software channels, that should be under
36 one hardware spinlock protection to prevent other systems from reading/writing
37 data by ADI software channels at the same time, or two parallel routine of setting
38 ADI registers will make ADI controller registers chaos to lead incorrect results.
39 Then we need one hardware spinlock to synchronize between the multiple subsystems.
41 The new version ADI controller supplies multiple master channels for different
42 subsystem accessing, that means no need to add hardware spinlock to synchronize,
43 thus change the hardware spinlock support to be optional to keep backward
47 - $ref: /spi/spi-controller.yaml#
66 $ref: /schemas/types.yaml#/definitions/uint32-matrix
67 description: A list of hardware channels
72 - description: The hardware channel id which is used to transfer data
73 triggered by hardware automatically, channel id 0-1 are for software
74 use, 2-49 are hardware channels.
77 - description: The analog chip address where user want to access by
86 unevaluatedProperties: false
94 adi_bus: spi@40030000 {
95 compatible = "sprd,sc9860-adi";
96 reg = <0 0x40030000 0 0x10000>;
97 hwlocks = <&hwlock1 0>;
101 sprd,hw-channels = <30 0x8c20>;