1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: "spi-controller.yaml#"
17 const: xlnx,zynqmp-qspi-1.0
40 unevaluatedProperties: false
44 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
50 compatible = "xlnx,zynqmp-qspi-1.0";
51 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
52 clock-names = "ref_clk", "pclk";
53 interrupts = <0 15 4>;
54 interrupt-parent = <&gic>;
55 reg = <0x0 0xff0f0000 0x0 0x1000>,
56 <0x0 0xc0000000 0x0 0x8000000>;