1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
15 properties are listed here. The controller specific properties should go in
16 their own separate schema that should be referenced from here.
19 - Mark Brown <broonie@kernel.org>
30 Chip select used by the device.
33 $ref: /schemas/types.yaml#/definitions/flag
35 The device requires the chip select active high.
38 $ref: /schemas/types.yaml#/definitions/flag
40 The device requires the LSB first mode.
43 $ref: /schemas/types.yaml#/definitions/uint32
45 Maximum SPI clocking speed of the device in Hz.
49 Bus width to the SPI bus used for read transfers.
50 If 0 is provided, then no RX will be possible on this device.
51 $ref: /schemas/types.yaml#/definitions/uint32
57 Delay, in microseconds, after a read transfer.
60 description: SPI Rx sample delay offset, unit is nanoseconds.
61 The delay from the default sample time before the actual
62 sample of the rxd input signal occurs.
66 Bus width to the SPI bus used for write transfers.
67 If 0 is provided, then no TX will be possible on this device.
68 $ref: /schemas/types.yaml#/definitions/uint32
74 Delay, in microseconds, after a write transfer.
77 description: Several SPI memories can be wired in stacked mode.
78 This basically means that either a device features several chip
79 selects, or that different devices must be seen as a single
80 bigger chip. This basically doubles (or more) the total address
81 space with only a single additional wire, while still needing
82 to repeat the commands when crossing a chip boundary. The size of
83 each chip should be provided as members of the array.
84 $ref: /schemas/types.yaml#/definitions/uint64-array
89 description: Several SPI memories can be wired in parallel mode.
90 The devices are physically on a different buses but will always
91 act synchronously as each data word is spread across the
92 different memories (eg. even bits are stored in one memory, odd
93 bits in the other). This basically doubles the address space and
94 the throughput while greatly complexifying the wiring because as
95 many busses as devices must be wired. The size of each chip should
96 be provided as members of the array.
97 $ref: /schemas/types.yaml#/definitions/uint64-array
101 # The controller specific properties go here.
103 - $ref: cdns,qspi-nor-peripheral-props.yaml#
104 - $ref: samsung,spi-peripheral-props.yaml#
105 - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
107 additionalProperties: true