1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
44 const: amd,pensando-elba-spi
47 - amd,pensando-elba-syscon
50 amd,pensando-elba-syscon: false
55 - description: Generic DW SPI Controller
59 - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
64 - const: snps,dw-apb-ssi
65 - description: Microchip Sparx5 SoC SPI Controller
66 const: microchip,sparx5-spi
67 - description: Amazon Alpine SPI Controller
68 const: amazon,alpine-dw-apb-ssi
69 - description: Renesas RZ/N1 SPI Controller
71 - const: renesas,rzn1-spi
72 - const: snps,dw-apb-ssi
73 - description: Intel Keem Bay SPI Controller
74 const: intel,keembay-ssi
75 - description: Intel Thunder Bay SPI Controller
76 const: intel,thunderbay-ssi
77 - description: Intel Mount Evans Integrated Management Complex SPI Controller
78 const: intel,mountevans-imc-ssi
79 - description: AMD Pensando Elba SoC SPI Controller
80 const: amd,pensando-elba-spi
81 - description: Baikal-T1 SPI Controller
83 - description: Baikal-T1 System Boot SPI Controller
84 const: baikal,bt1-sys-ssi
85 - description: Canaan Kendryte K210 SoS SPI Controller
86 const: canaan,k210-spi
87 - description: Renesas RZ/N1 SPI Controller
90 - renesas,r9a06g032-spi # RZ/N1D
91 - renesas,r9a06g033-spi # RZ/N1S
92 - const: renesas,rzn1-spi # RZ/N1
97 - description: DW APB SSI controller memory mapped registers
98 - description: SPI MST region map or directly mapped SPI ROM
106 - description: SPI Controller reference clock source
107 - description: APB interface clock source
122 description: I/O register width (in bytes) implemented by this device
133 - description: TX DMA Channel
134 - description: RX DMA Channel
144 Default value of the rx-sample-delay-ns property.
145 This value will be used if the property is not explicitly defined
146 for a SPI slave device.
148 SPI Rx sample delay offset, unit is nanoseconds.
149 The delay from the default sample time before the actual sample of the
150 rxd input signal occurs. The "rx_sample_delay" is an optional feature
151 of the designware controller, and the upper limit is also subject to
152 controller configuration.
154 amd,pensando-elba-syscon:
155 $ref: /schemas/types.yaml#/definitions/phandle-array
157 Block address to control SPI chip-selects. The Elba SoC system controller
158 provides an interface to override the native DWC SSI CS control.
163 additionalProperties: true
170 unevaluatedProperties: false
182 compatible = "snps,dw-apb-ssi";
183 reg = <0xfff00000 0x1000>;
184 #address-cells = <1>;
186 interrupts = <0 154 4>;
187 clocks = <&spi_m_clk>;
189 cs-gpios = <&gpio0 13 0>,
191 rx-sample-delay-ns = <3>;
193 compatible = "spi-nand";
195 rx-sample-delay-ns = <7>;
200 compatible = "baikal,bt1-sys-ssi";
201 reg = <0x1f040100 0x900>,
202 <0x1c000000 0x1000000>;
203 #address-cells = <1>;
205 mux-controls = <&boot_mux>;
207 clock-names = "ssi_clk";