1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas MSIOF SPI controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
24 - renesas,msiof-r8a7742 # RZ/G1H
25 - renesas,msiof-r8a7743 # RZ/G1M
26 - renesas,msiof-r8a7744 # RZ/G1N
27 - renesas,msiof-r8a7745 # RZ/G1E
28 - renesas,msiof-r8a77470 # RZ/G1C
29 - renesas,msiof-r8a7790 # R-Car H2
30 - renesas,msiof-r8a7791 # R-Car M2-W
31 - renesas,msiof-r8a7792 # R-Car V2H
32 - renesas,msiof-r8a7793 # R-Car M2-N
33 - renesas,msiof-r8a7794 # R-Car E2
34 - const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1
38 - renesas,msiof-r8a774a1 # RZ/G2M
39 - renesas,msiof-r8a774b1 # RZ/G2N
40 - renesas,msiof-r8a774c0 # RZ/G2E
41 - renesas,msiof-r8a774e1 # RZ/G2H
42 - renesas,msiof-r8a7795 # R-Car H3
43 - renesas,msiof-r8a7796 # R-Car M3-W
44 - renesas,msiof-r8a77961 # R-Car M3-W+
45 - renesas,msiof-r8a77965 # R-Car M3-N
46 - renesas,msiof-r8a77970 # R-Car V3M
47 - renesas,msiof-r8a77980 # R-Car V3H
48 - renesas,msiof-r8a77990 # R-Car E3
49 - renesas,msiof-r8a77995 # R-Car D3
50 - renesas,msiof-r8a779a0 # R-Car V3U
51 - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2
54 - const: renesas,sh-msiof # deprecated
61 - description: CPU and DMA engine registers
63 - description: CPU registers
64 - description: DMA engine registers
74 Total number of chip selects (default is 1).
75 Up to 3 native chip selects are supported:
79 Hardware limitations related to chip selects:
80 - Native chip selects are always deasserted in between transfers
81 that are part of the same message. Use cs-gpios to work around
83 - All slaves using native chip selects must use the same spi-cs-high
84 configuration. Use cs-gpios to work around this.
85 - When using GPIO chip selects, at least one native chip select must
86 be left unused, as it will be driven anyway.
102 description: delay sync signal (setup) in transmit mode.
103 $ref: /schemas/types.yaml#/definitions/uint32
106 - 50 # 0.5-clock-cycle delay
107 - 100 # 1-clock-cycle delay
108 - 150 # 1.5-clock-cycle delay
109 - 200 # 2-clock-cycle delay
112 description: delay sync signal (hold) in transmit mode
113 $ref: /schemas/types.yaml#/definitions/uint32
116 - 50 # 0.5-clock-cycle delay
117 - 100 # 1-clock-cycle delay
118 - 150 # 1.5-clock-cycle delay
119 - 200 # 2-clock-cycle delay
120 - 300 # 3-clock-cycle delay
122 renesas,tx-fifo-size:
123 # deprecated for soctype-specific bindings
125 Override the default TX fifo size. Unit is words. Ignored if 0.
126 $ref: /schemas/types.yaml#/definitions/uint32
130 renesas,rx-fifo-size:
131 # deprecated for soctype-specific bindings
133 Override the default RX fifo size. Unit is words. Ignored if 0.
134 $ref: /schemas/types.yaml#/definitions/uint32
145 unevaluatedProperties: false
149 #include <dt-bindings/clock/r8a7791-clock.h>
150 #include <dt-bindings/interrupt-controller/irq.h>
152 msiof0: spi@e6e20000 {
153 compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
154 reg = <0xe6e20000 0x0064>;
155 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
157 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
158 dma-names = "tx", "rx";
159 #address-cells = <1>;