1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 - $ref: "spi-controller.yaml#"
19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
22 - nvidia,tegra234-qspi
60 nvidia,tx-clk-tap-delay:
62 Delays the clock going out to device with this tap value.
63 Tap value varies based on platform design trace lengths from Tegra
64 QSPI to corresponding slave device.
65 $ref: /schemas/types.yaml#/definitions/uint32
69 nvidia,rx-clk-tap-delay:
71 Delays the clock coming in from the device with this tap value.
72 Tap value varies based on platform design trace lengths from Tegra
73 QSPI to corresponding slave device.
74 $ref: /schemas/types.yaml#/definitions/uint32
89 unevaluatedProperties: false
93 #include <dt-bindings/clock/tegra210-car.h>
94 #include <dt-bindings/reset/tegra210-car.h>
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 compatible = "nvidia,tegra210-qspi";
98 reg = <0x70410000 0x1000>;
99 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
102 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
103 <&tegra_car TEGRA210_CLK_QSPI_PM>;
104 clock-names = "qspi", "qspi_out";
105 resets = <&tegra_car 211>;
106 dmas = <&apbdma 5>, <&apbdma 5>;
107 dma-names = "rx", "tx";
110 compatible = "jedec,spi-nor";
112 spi-max-frequency = <104000000>;
113 spi-tx-bus-width = <2>;
114 spi-rx-bus-width = <2>;
115 nvidia,tx-clk-tap-delay = <0>;
116 nvidia,rx-clk-tap-delay = <0>;