Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SPI-NAND flash controller for MediaTek ARM SoCs
   8
   9 maintainers:
  10   - Chuanhong Guo <gch981213@gmail.com>
  11
  12 description: |
  13   The Mediatek SPI-NAND flash controller is an extended version of
  14   the Mediatek NAND flash controller. It can perform standard SPI
  15   instructions with one continuous write and one read for up-to 0xa0
  16   bytes. It also supports typical SPI-NAND page cache operations
  17   in single, dual or quad IO mode with pipelined ECC encoding/decoding
  18   using the accompanying ECC engine. There should be only one spi
  19   slave device following generic spi bindings.
  20
  21 allOf:
  22   - $ref: /schemas/spi/spi-controller.yaml#
  23
  24 properties:
  25   compatible:
  26     enum:
  27       - mediatek,mt7622-snand
  28       - mediatek,mt7629-snand
  29
  30   reg:
  31     items:
  32       - description: core registers
  33
  34   interrupts:
  35     items:
  36       - description: NFI interrupt
  37
  38   clocks:
  39     items:
  40       - description: clock used for the controller
  41       - description: clock used for the SPI bus
  42
  43   clock-names:
  44     items:
  45       - const: nfi_clk
  46       - const: pad_clk
  47
  48   nand-ecc-engine:
  49     description: device-tree node of the accompanying ECC engine.
  50     $ref: /schemas/types.yaml#/definitions/phandle
  51
  52 required:
  53   - compatible
  54   - reg
  55   - interrupts
  56   - clocks
  57   - clock-names
  58   - nand-ecc-engine
  59
  60 unevaluatedProperties: false
  61
  62 examples:
  63   - |
  64     #include <dt-bindings/interrupt-controller/irq.h>
  65     #include <dt-bindings/interrupt-controller/arm-gic.h>
  66     #include <dt-bindings/clock/mt7622-clk.h>
  67     soc {
  68       #address-cells = <2>;
  69       #size-cells = <2>;
  70       snfi: spi@1100d000 {
  71         compatible = "mediatek,mt7622-snand";
  72         reg = <0 0x1100d000 0 0x1000>;
  73         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
  74         clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
  75         clock-names = "nfi_clk", "pad_clk";
  76         nand-ecc-engine = <&bch>;
  77         #address-cells = <1>;
  78         #size-cells = <0>;
  79
  80         flash@0 {
  81           compatible = "spi-nand";
  82           reg = <0>;
  83           spi-tx-bus-width = <4>;
  84           spi-rx-bus-width = <4>;
  85           nand-ecc-engine = <&snfi>;
  86         };
  87       };
  88     };