Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Serial NOR flash controller for MediaTek ARM SoCs
   8
   9 maintainers:
  10   - Bayi Cheng <bayi.cheng@mediatek.com>
  11   - Chuanhong Guo <gch981213@gmail.com>
  12
  13 description: |
  14   This spi controller support single, dual, or quad mode transfer for
  15   SPI NOR flash. There should be only one spi slave device following
  16   generic spi bindings. It's not recommended to use this controller
  17   for devices other than SPI NOR flash due to limited transfer
  18   capability of this controller.
  19
  20 allOf:
  21   - $ref: /spi/spi-controller.yaml#
  22
  23 properties:
  24   compatible:
  25     oneOf:
  26       - items:
  27           - enum:
  28               - mediatek,mt2701-nor
  29               - mediatek,mt2712-nor
  30               - mediatek,mt7622-nor
  31               - mediatek,mt7623-nor
  32               - mediatek,mt7629-nor
  33               - mediatek,mt8192-nor
  34           - enum:
  35               - mediatek,mt8173-nor
  36       - items:
  37           - const: mediatek,mt8173-nor
  38   reg:
  39     maxItems: 1
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   clocks:
  45     items:
  46       - description: clock used for spi bus
  47       - description: clock used for controller
  48
  49   clock-names:
  50     items:
  51       - const: spi
  52       - const: sf
  53
  54 required:
  55   - compatible
  56   - reg
  57   - interrupts
  58   - clocks
  59   - clock-names
  60
  61 unevaluatedProperties: false
  62
  63 examples:
  64   - |
  65     #include <dt-bindings/clock/mt8173-clk.h>
  66
  67     soc {
  68       #address-cells = <2>;
  69       #size-cells = <2>;
  70
  71       nor_flash: spi@1100d000 {
  72         compatible = "mediatek,mt8173-nor";
  73         reg = <0 0x1100d000 0 0xe0>;
  74         interrupts = <&spi_flash_irq>;
  75         clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
  76         clock-names = "spi", "sf";
  77         #address-cells = <1>;
  78         #size-cells = <0>;
  79
  80         flash@0 {
  81           compatible = "jedec,spi-nor";
  82           reg = <0>;
  83         };
  84       };
  85     };
  86