1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: "/schemas/spi/spi-controller.yaml#"
21 - const: mediatek,mt7622-spi
25 - const: mediatek,mt2712-spi
32 - const: mediatek,mt6765-spi
35 - mediatek,mt7986-spi-ipm
36 - const: mediatek,spi-ipm
58 - description: clock used for the parent clock
59 - description: clock used for the muxes clock
60 - description: clock used for the clock gate
61 - description: clock used for the AHB bus, this clock is optional
72 $ref: /schemas/types.yaml#/definitions/uint32-array
78 specify which pins group(ck/mi/mo/cs) spi controller used.
90 unevaluatedProperties: false
94 #include <dt-bindings/clock/mt8173-clk.h>
95 #include <dt-bindings/gpio/gpio.h>
96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 #include <dt-bindings/interrupt-controller/irq.h>
100 compatible = "mediatek,mt8173-spi";
101 #address-cells = <1>;
103 reg = <0x1100a000 0x1000>;
104 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
105 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
106 <&topckgen CLK_TOP_SPI_SEL>,
107 <&pericfg CLK_PERI_SPI0>;
108 clock-names = "parent-clk", "sel-clk", "spi-clk";
109 cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
110 mediatek,pad-select = <1>, <0>;