Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Cadence Quad SPI controller
   8
   9 maintainers:
  10   - Vaishnav Achath <vaishnav.a@ti.com>
  11
  12 allOf:
  13   - $ref: spi-controller.yaml#
  14   - if:
  15       properties:
  16         compatible:
  17           contains:
  18             const: xlnx,versal-ospi-1.0
  19     then:
  20       required:
  21         - power-domains
  22   - if:
  23       properties:
  24         compatible:
  25           contains:
  26             const: starfive,jh7110-qspi
  27     then:
  28       properties:
  29         resets:
  30           minItems: 2
  31           maxItems: 3
  32
  33         reset-names:
  34           minItems: 2
  35           maxItems: 3
  36           items:
  37             enum: [ qspi, qspi-ocp, rstc_ref ]
  38
  39     else:
  40       properties:
  41         resets:
  42           maxItems: 2
  43
  44         reset-names:
  45           minItems: 1
  46           maxItems: 2
  47           items:
  48             enum: [ qspi, qspi-ocp ]
  49   - if:
  50       properties:
  51         compatible:
  52           contains:
  53             const: amd,pensando-elba-qspi
  54     then:
  55       properties:
  56         cdns,fifo-depth:
  57           enum: [ 128, 256, 1024 ]
  58           default: 1024
  59     else:
  60       properties:
  61         cdns,fifo-depth:
  62           enum: [ 128, 256 ]
  63           default: 128
  64
  65 properties:
  66   compatible:
  67     oneOf:
  68       - items:
  69           - enum:
  70               - amd,pensando-elba-qspi
  71               - ti,k2g-qspi
  72               - ti,am654-ospi
  73               - intel,lgm-qspi
  74               - xlnx,versal-ospi-1.0
  75               - intel,socfpga-qspi
  76               - starfive,jh7110-qspi
  77           - const: cdns,qspi-nor
  78       - const: cdns,qspi-nor
  79
  80   reg:
  81     items:
  82       - description: the controller register set
  83       - description: the controller data area
  84
  85   interrupts:
  86     maxItems: 1
  87
  88   clocks:
  89     minItems: 1
  90     maxItems: 3
  91
  92   clock-names:
  93     oneOf:
  94       - items:
  95           - const: ref
  96       - items:
  97           - const: ref
  98           - const: ahb
  99           - const: apb
 100
 101   cdns,fifo-depth:
 102     description:
 103       Size of the data FIFO in words.
 104     $ref: /schemas/types.yaml#/definitions/uint32
 105
 106   cdns,fifo-width:
 107     $ref: /schemas/types.yaml#/definitions/uint32
 108     description:
 109       Bus width of the data FIFO in bytes.
 110     default: 4
 111
 112   cdns,trigger-address:
 113     $ref: /schemas/types.yaml#/definitions/uint32
 114     description:
 115       32-bit indirect AHB trigger address.
 116
 117   cdns,is-decoded-cs:
 118     type: boolean
 119     description:
 120       Flag to indicate whether decoder is used to select different chip select
 121       for different memory regions.
 122
 123   cdns,rclk-en:
 124     type: boolean
 125     description:
 126       Flag to indicate that QSPI return clock is used to latch the read
 127       data rather than the QSPI clock. Make sure that QSPI return clock
 128       is populated on the board before using this property.
 129
 130   power-domains:
 131     maxItems: 1
 132
 133   resets:
 134     minItems: 2
 135     maxItems: 3
 136
 137   reset-names:
 138     minItems: 2
 139     maxItems: 3
 140     items:
 141       enum: [ qspi, qspi-ocp, rstc_ref ]
 142
 143 required:
 144   - compatible
 145   - reg
 146   - interrupts
 147   - clocks
 148   - cdns,fifo-depth
 149   - cdns,fifo-width
 150   - cdns,trigger-address
 151   - '#address-cells'
 152   - '#size-cells'
 153
 154 unevaluatedProperties: false
 155
 156 examples:
 157   - |
 158     qspi: spi@ff705000 {
 159         compatible = "cdns,qspi-nor";
 160         #address-cells = <1>;
 161         #size-cells = <0>;
 162         reg = <0xff705000 0x1000>,
 163               <0xffa00000 0x1000>;
 164         interrupts = <0 151 4>;
 165         clocks = <&qspi_clk>;
 166         cdns,fifo-depth = <128>;
 167         cdns,fifo-width = <4>;
 168         cdns,trigger-address = <0x00000000>;
 169         resets = <&rst 0x1>, <&rst 0x2>;
 170         reset-names = "qspi", "qspi-ocp";
 171
 172         flash@0 {
 173             compatible = "jedec,spi-nor";
 174             reg = <0x0>;
 175         };
 176     };