Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Cadence Quad SPI controller
   8
   9 maintainers:
  10   - Vaishnav Achath <vaishnav.a@ti.com>
  11
  12 allOf:
  13   - $ref: spi-controller.yaml#
  14   - if:
  15       properties:
  16         compatible:
  17           contains:
  18             const: xlnx,versal-ospi-1.0
  19     then:
  20       required:
  21         - power-domains
  22
  23 properties:
  24   compatible:
  25     oneOf:
  26       - items:
  27           - enum:
  28               - ti,k2g-qspi
  29               - ti,am654-ospi
  30               - intel,lgm-qspi
  31               - xlnx,versal-ospi-1.0
  32               - intel,socfpga-qspi
  33           - const: cdns,qspi-nor
  34       - const: cdns,qspi-nor
  35
  36   reg:
  37     items:
  38       - description: the controller register set
  39       - description: the controller data area
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   clocks:
  45     maxItems: 1
  46
  47   cdns,fifo-depth:
  48     description:
  49       Size of the data FIFO in words.
  50     $ref: "/schemas/types.yaml#/definitions/uint32"
  51     enum: [ 128, 256 ]
  52     default: 128
  53
  54   cdns,fifo-width:
  55     $ref: /schemas/types.yaml#/definitions/uint32
  56     description:
  57       Bus width of the data FIFO in bytes.
  58     default: 4
  59
  60   cdns,trigger-address:
  61     $ref: /schemas/types.yaml#/definitions/uint32
  62     description:
  63       32-bit indirect AHB trigger address.
  64
  65   cdns,is-decoded-cs:
  66     type: boolean
  67     description:
  68       Flag to indicate whether decoder is used to select different chip select
  69       for different memory regions.
  70
  71   cdns,rclk-en:
  72     type: boolean
  73     description:
  74       Flag to indicate that QSPI return clock is used to latch the read
  75       data rather than the QSPI clock. Make sure that QSPI return clock
  76       is populated on the board before using this property.
  77
  78   power-domains:
  79     maxItems: 1
  80
  81   resets:
  82     maxItems: 2
  83
  84   reset-names:
  85     minItems: 1
  86     maxItems: 2
  87     items:
  88       enum: [ qspi, qspi-ocp ]
  89
  90 required:
  91   - compatible
  92   - reg
  93   - interrupts
  94   - clocks
  95   - cdns,fifo-depth
  96   - cdns,fifo-width
  97   - cdns,trigger-address
  98   - '#address-cells'
  99   - '#size-cells'
 100
 101 unevaluatedProperties: false
 102
 103 examples:
 104   - |
 105     qspi: spi@ff705000 {
 106       compatible = "cdns,qspi-nor";
 107       #address-cells = <1>;
 108       #size-cells = <0>;
 109       reg = <0xff705000 0x1000>,
 110             <0xffa00000 0x1000>;
 111       interrupts = <0 151 4>;
 112       clocks = <&qspi_clk>;
 113       cdns,fifo-depth = <128>;
 114       cdns,fifo-width = <4>;
 115       cdns,trigger-address = <0x00000000>;
 116       resets = <&rst 0x1>, <&rst 0x2>;
 117       reset-names = "qspi", "qspi-ocp";
 118
 119       flash@0 {
 120               compatible = "jedec,spi-nor";
 121               reg = <0x0>;
 122       };
 123     };