GNU Linux-libre 4.14.266-gnu1
[releases.git] / Documentation / devicetree / bindings / spi / brcm,spi-bcm-qspi.txt
1 Broadcom SPI controller
2
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
5 of :
6  MSPI : SPI master controller can read and write to a SPI slave device
7  BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
8         for flash reads and be configured to do single, double, quad lane
9         io with 3-byte and 4-byte addressing support.
10
11  Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
12  MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
13  of a MSPI master without the BSPI to use with non flash slave devices that
14  use SPI protocol.
15
16 Required properties:
17
18 - #address-cells:
19     Must be <1>, as required by generic SPI binding.
20
21 - #size-cells:
22     Must be <0>, also as required by generic SPI binding.
23
24 - compatible:
25     Must be one of :
26     "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
27     "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
28                                                    BRCMSTB  SoCs
29     "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"     : MSPI+BSPI on Cygnus, NSP
30     "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"     : NS2 SoCs
31
32 - reg:
33     Define the bases and ranges of the associated I/O address spaces.
34     The required range is MSPI controller registers.
35
36 - reg-names:
37     First name does not matter, but must be reserved for the MSPI controller
38     register range as mentioned in 'reg' above, and will typically contain
39     - "bspi_regs": BSPI register range, not required with compatible
40                    "spi-brcmstb-mspi"
41     - "mspi_regs": MSPI register range is required for compatible strings
42     - "intr_regs", "intr_status_reg" : Interrupt and status register for
43       NSP, NS2, Cygnus SoC
44
45 - interrupts
46     The interrupts used by the MSPI and/or BSPI controller.
47
48 - interrupt-names:
49     Names of interrupts associated with MSPI
50     - "mspi_halted" :
51     - "mspi_done": Indicates that the requested SPI operation is complete.
52     - "spi_lr_fullness_reached" : Linear read BSPI pipe full
53     - "spi_lr_session_aborted"  : Linear read BSPI pipe aborted
54     - "spi_lr_impatient" : Linear read BSPI requested when pipe empty
55     - "spi_lr_session_done" : Linear read BSPI session done
56
57 - clocks:
58     A phandle to the reference clock for this block.
59
60 Optional properties:
61
62
63 - native-endian
64     Defined when using BE SoC and device uses BE register read/write
65
66 Recommended optional m25p80 properties:
67 - spi-rx-bus-width: Definition as per
68                     Documentation/devicetree/bindings/spi/spi-bus.txt
69
70 Examples:
71
72 BRCMSTB SoC Example:
73
74   SPI Master (MSPI+BSPI) for SPI-NOR access:
75
76     spi@f03e3400 {
77                 #address-cells = <0x1>;
78                 #size-cells = <0x0>;
79                 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi";
80                 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
81                 reg-names = "cs_reg", "mspi", "bspi";
82                 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
83                 interrupt-parent = <0x1c>;
84                 interrupt-names = "mspi_halted",
85                                   "mspi_done",
86                                   "spi_lr_overread",
87                                   "spi_lr_session_done",
88                                   "spi_lr_impatient",
89                                   "spi_lr_session_aborted",
90                                   "spi_lr_fullness_reached";
91
92                 clocks = <&hif_spi>;
93                 clock-names = "sw_spi";
94
95                 m25p80@0 {
96                         #size-cells = <0x2>;
97                         #address-cells = <0x2>;
98                         compatible = "m25p80";
99                         reg = <0x0>;
100                         spi-max-frequency = <0x2625a00>;
101                         spi-cpol;
102                         spi-cpha;
103                         m25p,fast-read;
104
105                         flash0.bolt@0 {
106                                 reg = <0x0 0x0 0x0 0x100000>;
107                         };
108
109                         flash0.macadr@100000 {
110                                 reg = <0x0 0x100000 0x0 0x10000>;
111                         };
112
113                         flash0.nvram@110000 {
114                                 reg = <0x0 0x110000 0x0 0x10000>;
115                         };
116
117                         flash0.kernel@120000 {
118                                 reg = <0x0 0x120000 0x0 0x400000>;
119                         };
120
121                         flash0.devtree@520000 {
122                                 reg = <0x0 0x520000 0x0 0x10000>;
123                         };
124
125                         flash0.splash@530000 {
126                                 reg = <0x0 0x530000 0x0 0x80000>;
127                         };
128
129                         flash0@0 {
130                                 reg = <0x0 0x0 0x0 0x4000000>;
131                         };
132                 };
133         };
134
135
136     MSPI master for any SPI device :
137
138         spi@f0416000 {
139                 #address-cells = <1>;
140                 #size-cells = <0>;
141                 clocks = <&upg_fixed>;
142                 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi";
143                 reg = <0xf0416000 0x180>;
144                 reg-names = "mspi";
145                 interrupts = <0x14>;
146                 interrupt-parent = <&irq0_aon_intc>;
147                 interrupt-names = "mspi_done";
148         };
149
150 iProc SoC Example:
151
152     qspi: spi@18027200 {
153         compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
154         reg = <0x18027200 0x184>,
155               <0x18027000 0x124>,
156               <0x1811c408 0x004>,
157               <0x180273a0 0x01c>;
158         reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg";
159         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
160                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
161                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
162                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
163                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
164                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
165                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
166         interrupt-names =
167                      "spi_lr_fullness_reached",
168                      "spi_lr_session_aborted",
169                      "spi_lr_impatient",
170                      "spi_lr_session_done",
171                      "mspi_done",
172                      "mspi_halted";
173         clocks = <&iprocmed>;
174         clock-names = "iprocmed";
175         num-cs = <2>;
176         #address-cells = <1>;
177         #size-cells = <0>;
178     };
179
180
181  NS2 SoC Example:
182
183                qspi: spi@66470200 {
184                        compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
185                        reg = <0x66470200 0x184>,
186                              <0x66470000 0x124>,
187                              <0x67017408 0x004>,
188                              <0x664703a0 0x01c>;
189                        reg-names = "mspi", "bspi", "intr_regs",
190                         "intr_status_reg";
191                        interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
192                        interrupt-names = "spi_l1_intr";
193                         clocks = <&iprocmed>;
194                         clock-names = "iprocmed";
195                         num-cs = <2>;
196                         #address-cells = <1>;
197                         #size-cells = <0>;
198                };
199
200
201  m25p80 node for NSP, NS2
202
203          &qspi {
204                       flash: m25p80@0 {
205                       #address-cells = <1>;
206                       #size-cells = <1>;
207                       compatible = "m25p80";
208                       reg = <0x0>;
209                       spi-max-frequency = <12500000>;
210                       m25p,fast-read;
211                       spi-cpol;
212                       spi-cpha;
213
214                       partition@0 {
215                                   label = "boot";
216                                   reg = <0x00000000 0x000a0000>;
217                       };
218
219                       partition@a0000 {
220                                   label = "env";
221                                   reg = <0x000a0000 0x00060000>;
222                       };
223
224                       partition@100000 {
225                                   label = "system";
226                                   reg = <0x00100000 0x00600000>;
227                       };
228
229                       partition@700000 {
230                                   label = "rootfs";
231                                   reg = <0x00700000 0x01900000>;
232                       };
233         };