1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra210 ADMAIF Device Tree Bindings
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
11 that sends/receives data to/from AHUB must interface through an
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
31 - nvidia,tegra234-admaif
32 - nvidia,tegra194-admaif
33 - const: nvidia,tegra186-admaif
43 $ref: /schemas/graph.yaml#/properties/ports
45 Contains list of ACIF (Audio CIF) port nodes for ADMAIF channels.
46 The number of port nodes depends on the number of ADMAIF channels
47 that SoC may have. These are interfaced with respective ACIF ports
48 in AHUB (Audio Hub). Each port is capable of data transfers in
53 $ref: audio-graph-port.yaml#
54 unevaluatedProperties: false
60 const: nvidia,tegra210-admaif
66 DMA channel specifiers, equally divided for Tx and Rx.
71 pattern: "^[rt]x(10|[1-9])$"
73 Should be "rx1", "rx2" ... "rx10" for DMA Rx channel
74 Should be "tx1", "tx2" ... "tx10" for DMA Tx channel
82 DMA channel specifiers, equally divided for Tx and Rx.
87 pattern: "^[rt]x(1[0-9]|[1-9]|20)$"
89 Should be "rx1", "rx2" ... "rx20" for DMA Rx channel
90 Should be "tx1", "tx2" ... "tx20" for DMA Tx channel
100 additionalProperties: false
105 compatible = "nvidia,tegra210-admaif";
106 reg = <0x702d0000 0x800>;
107 dmas = <&adma 1>, <&adma 1>,
108 <&adma 2>, <&adma 2>,
109 <&adma 3>, <&adma 3>,
110 <&adma 4>, <&adma 4>,
111 <&adma 5>, <&adma 5>,
112 <&adma 6>, <&adma 6>,
113 <&adma 7>, <&adma 7>,
114 <&adma 8>, <&adma 8>,
115 <&adma 9>, <&adma 9>,
116 <&adma 10>, <&adma 10>;
117 dma-names = "rx1", "tx1",