1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8195
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
23 $ref: "/schemas/types.yaml#/definitions/phandle"
24 description: The phandle of the mediatek topckgen controller
31 - description: 26M clock
32 - description: audio pll1 clock
33 - description: audio pll2 clock
34 - description: clock divider for i2si1_mck
35 - description: clock divider for i2si2_mck
36 - description: clock divider for i2so1_mck
37 - description: clock divider for i2so2_mck
38 - description: clock divider for dptx_mck
39 - description: a1sys hoping clock
40 - description: audio intbus clock
41 - description: audio hires clock
42 - description: audio local bus clock
43 - description: mux for dptx_mck
44 - description: mux for i2so1_mck
45 - description: mux for i2so2_mck
46 - description: mux for i2si1_mck
47 - description: mux for i2si2_mck
48 - description: audio infra 26M clock
49 - description: infra bus clock
62 - const: aud_intbus_sel
64 - const: audio_local_bus_sel
70 - const: infra_ao_audio_26m_b
71 - const: scp_adsp_audiodsp
73 mediatek,etdm-in1-chn-disabled:
74 $ref: /schemas/types.yaml#/definitions/uint8-array
76 description: Specify which input channel should be disabled.
78 mediatek,etdm-in2-chn-disabled:
79 $ref: /schemas/types.yaml#/definitions/uint8-array
81 description: Specify which input channel should be disabled.
84 "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
85 description: Specify etdm in mclk output rate for always on case.
87 "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
88 description: Specify etdm out mclk output rate for always on case.
90 "^mediatek,etdm-in[1-2]-multi-pin-mode$":
92 description: if present, the etdm data mode is I2S.
94 "^mediatek,etdm-out[1-3]-multi-pin-mode$":
96 description: if present, the etdm data mode is I2S.
98 "^mediatek,etdm-in[1-2]-cowork-source$":
99 $ref: /schemas/types.yaml#/definitions/uint32
101 etdm modules can share the same external clock pin. Specify
102 which etdm clock source is required by this etdm in moudule.
109 "^mediatek,etdm-out[1-2]-cowork-source$":
110 $ref: /schemas/types.yaml#/definitions/uint32
112 etdm modules can share the same external clock pin. Specify
113 which etdm clock source is required by this etdm out moudule.
129 additionalProperties: false
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
134 #include <dt-bindings/interrupt-controller/irq.h>
136 afe: mt8195-afe-pcm@10890000 {
137 compatible = "mediatek,mt8195-audio";
138 reg = <0x10890000 0x10000>;
139 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
140 mediatek,topckgen = <&topckgen>;
141 power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
143 <&topckgen 163>, //CLK_TOP_APLL1
144 <&topckgen 166>, //CLK_TOP_APLL2
145 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
146 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
147 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
148 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
149 <&topckgen 238>, //CLK_TOP_APLL12_DIV9
150 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
151 <&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL
152 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL
153 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL
154 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL
155 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL
156 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL
157 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL
158 <&topckgen 97>, //CLK_TOP_I2SI2_M_SEL
159 <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B
160 <&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP
161 clock-names = "clk26m",
172 "audio_local_bus_sel",
178 "infra_ao_audio_26m_b",