1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek AFE PCM controller for MT7986
10 - Maso Huang <maso.huang@mediatek.com>
15 - const: mediatek,mt7986-afe
20 - const: mediatek,mt7986-afe
31 - description: audio bus clock
32 - description: audio 26M clock
33 - description: audio intbus clock
34 - description: audio hopping clock
35 - description: audio pll clock
36 - description: mux for pcm_mck
37 - description: audio i2s/pcm mck
62 const: mediatek,mt7986-afe
67 - description: audio bus clock
68 - description: audio 26M clock
69 - description: audio intbus clock
70 - description: audio hopping clock
71 - description: audio pll clock
84 const: mediatek,mt7981-afe
89 - description: audio bus clock
90 - description: audio 26M clock
91 - description: audio intbus clock
92 - description: audio hopping clock
93 - description: audio pll clock
94 - description: mux for pcm_mck
108 const: mediatek,mt7988-afe
113 - description: audio bus clock
114 - description: audio 26M clock
115 - description: audio intbus clock
116 - description: audio hopping clock
117 - description: audio pll clock
118 - description: mux for pcm_mck
119 - description: audio i2s/pcm mck
130 additionalProperties: false
134 #include <dt-bindings/interrupt-controller/arm-gic.h>
135 #include <dt-bindings/interrupt-controller/irq.h>
136 #include <dt-bindings/clock/mt7986-clk.h>
139 compatible = "mediatek,mt7986-afe";
140 reg = <0x11210000 0x9000>;
141 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
143 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
144 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
145 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
146 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
147 clock-names = "bus_ck",
152 assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
153 <&topckgen CLK_TOP_AUD_L_SEL>,
154 <&topckgen CLK_TOP_A_TUNER_SEL>;
155 assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
156 <&apmixedsys CLK_APMIXED_APLL2>,
157 <&topckgen CLK_TOP_APLL2_D4>;