1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 The Freescale S/PDIF audio block is a stereo transceiver that allows the
14 processor to receive and transmit digital audio via an coaxial cable or
38 - description: DMA controller phandle and request line for RX
39 - description: DMA controller phandle and request line for TX
48 - description: The core clock of spdif controller.
49 - description: Clock for tx0 and rx0.
50 - description: Clock for tx1 and rx1.
51 - description: Clock for tx2 and rx2.
52 - description: Clock for tx3 and rx3.
53 - description: Clock for tx4 and rx4.
54 - description: Clock for tx5 and rx5.
55 - description: Clock for tx6 and rx6.
56 - description: Clock for tx7 and rx7.
57 - description: The spba clock is required when SPDIF is placed as a bus
58 slave of the Shared Peripheral Bus and when two or more bus masters
59 (CPU, DMA or DSP) try to access it. This property is optional depending
61 - description: PLL clock source for 8kHz series rate, optional.
62 - description: PLL clock source for 11khz series rate, optional.
82 $ref: /schemas/types.yaml#/definitions/flag
84 If this property is absent, the native endian mode will be in use
85 as default, or the big endian mode will be in use for all the device
86 registers. Set this flag for HCDs with big endian descriptors and big
98 additionalProperties: false
103 compatible = "fsl,imx35-spdif";
104 reg = <0x02004000 0x4000>;
105 interrupts = <0 52 0x04>;
106 dmas = <&sdma 14 18 0>,
108 dma-names = "rx", "tx";
109 clocks = <&clks 197>, <&clks 3>,
110 <&clks 197>, <&clks 107>,
111 <&clks 0>, <&clks 118>,
112 <&clks 62>, <&clks 139>,
114 clock-names = "core", "rxtx0",