1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Synchronous Audio Interface (SAI).
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
34 - const: fsl,imx8mq-sai
41 - description: receive and transmit interrupt
51 - description: The ipg clock for register access
52 - description: master clock source 0 (obsoleted)
53 - description: master clock source 1
54 - description: master clock source 2
55 - description: master clock source 3
56 - description: PLL clock source for 8kHz series
57 - description: PLL clock source for 11kHz series
82 Configures whether the LSB or the MSB is transmitted
83 first for the fifo data. If this property is absent,
84 the MSB is transmitted first as default, or the LSB
90 required if all the SAI registers are big-endian rather than little-endian.
93 fsl,sai-synchronous-rx:
95 SAI will work in the synchronous mode (sync Tx with Rx) which means
96 both the transmitter and the receiver will send and receive data by
97 following receiver's bit clocks and frame sync clocks.
100 fsl,sai-asynchronous:
102 SAI will work in the asynchronous mode, which means both transmitter
103 and receiver will send and receive data by following their own bit clocks
104 and frame sync clocks separately.
105 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
106 default synchronous mode (sync Rx with Tx) will be used, which means both
107 transmitter and receiver will send and receive data by following clocks
112 $ref: /schemas/types.yaml#/definitions/uint32-matrix
114 Configure the dataline. It has 3 value for each configuration
118 - description: format Default(0), I2S(1) or PDM(2)
120 - description: dataline mask for 'rx'
121 - description: dataline mask for 'tx'
123 fsl,sai-mclk-direction-output:
124 description: SAI will output the SAI MCLK clock.
127 fsl,shared-interrupt:
128 description: Interrupt is shared with other modules.
133 description: optional, some dts node didn't add it.
145 - description: DMA controller phandle and request line for TX
146 - description: DMA controller phandle and request line for RX
155 - description: DMA controller phandle and request line for RX
156 - description: DMA controller phandle and request line for TX
163 - fsl,sai-asynchronous
166 fsl,sai-synchronous-rx: false
177 additionalProperties: false
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/vf610-clock.h>
184 compatible = "fsl,vf610-sai";
185 reg = <0x40031000 0x1000>;
186 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_sai2_1>;
189 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
190 <&clks VF610_CLK_SAI2>,
191 <&clks 0>, <&clks 0>;
192 clock-names = "bus", "mclk1", "mclk2", "mclk3";
193 dma-names = "tx", "rx";
194 dmas = <&edma0 0 21>,
201 #include <dt-bindings/interrupt-controller/arm-gic.h>
202 #include <dt-bindings/clock/imx8mm-clock.h>
204 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
205 reg = <0x30010000 0x10000>;
206 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
208 <&clk IMX8MM_CLK_DUMMY>,
209 <&clk IMX8MM_CLK_SAI1_ROOT>,
210 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
211 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
212 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
213 dma-names = "rx", "tx";
214 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
215 #sound-dai-cells = <0>;