1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Synchronous Audio Interface (SAI).
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
25 - const: fsl,imx6sx-sai
32 - const: fsl,imx8mq-sai
49 - description: The ipg clock for register access
50 - description: master clock source 0 (obsoleted)
51 - description: master clock source 1
52 - description: master clock source 2
53 - description: master clock source 3
54 - description: PLL clock source for 8kHz series
55 - description: PLL clock source for 11kHz series
80 - description: DMA controller phandle and request line for RX
81 - description: DMA controller phandle and request line for TX
90 - description: receive and transmit interrupt
94 required if all the SAI registers are big-endian rather than little-endian.
98 $ref: /schemas/types.yaml#/definitions/uint32-matrix
100 Configure the dataline. It has 3 value for each configuration
104 - description: format Default(0), I2S(1) or PDM(2)
106 - description: dataline mask for 'rx'
107 - description: dataline mask for 'tx'
109 fsl,sai-mclk-direction-output:
110 description: SAI will output the SAI MCLK clock.
113 fsl,sai-synchronous-rx:
115 SAI will work in the synchronous mode (sync Tx with Rx) which means
116 both the transmitter and the receiver will send and receive data by
117 following receiver's bit clocks and frame sync clocks.
120 fsl,sai-asynchronous:
122 SAI will work in the asynchronous mode, which means both transmitter
123 and receiver will send and receive data by following their own bit clocks
124 and frame sync clocks separately.
125 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
126 default synchronous mode (sync Rx with Tx) will be used, which means both
127 transmitter and receiver will send and receive data by following clocks
131 fsl,shared-interrupt:
132 description: Interrupt is shared with other modules.
137 Configures whether the LSB or the MSB is transmitted
138 first for the fifo data. If this property is absent,
139 the MSB is transmitted first as default, or the LSB
140 is transmitted first.
145 description: optional, some dts node didn't add it.
148 - $ref: dai-common.yaml#
151 - fsl,sai-asynchronous
154 fsl,sai-synchronous-rx: false
165 unevaluatedProperties: false
169 #include <dt-bindings/interrupt-controller/arm-gic.h>
170 #include <dt-bindings/clock/vf610-clock.h>
172 compatible = "fsl,vf610-sai";
173 reg = <0x40031000 0x1000>;
174 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_sai2_1>;
177 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
178 <&clks VF610_CLK_SAI2>,
179 <&clks 0>, <&clks 0>;
180 clock-names = "bus", "mclk1", "mclk2", "mclk3";
181 dma-names = "rx", "tx";
182 dmas = <&edma0 0 20>, <&edma0 0 21>;
188 #include <dt-bindings/interrupt-controller/arm-gic.h>
189 #include <dt-bindings/clock/imx8mm-clock.h>
191 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
192 reg = <0x30010000 0x10000>;
193 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
195 <&clk IMX8MM_CLK_DUMMY>,
196 <&clk IMX8MM_CLK_SAI1_ROOT>,
197 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
198 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
199 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
200 dma-names = "rx", "tx";
201 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
202 #sound-dai-cells = <0>;