Documentation/devicetree/bindings/sound/atmel,sama5d2-i2s.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-i2s.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Atmel I2S controller
   9
  10 maintainers:
  11   - Nicolas Ferre <nicolas.ferre@microchip.com>
  12   - Alexandre Belloni <alexandre.belloni@bootlin.com>
  13   - Claudiu Beznea <claudiu.beznea@microchip.com>
  14
  15 description:
  16   Atmel I2S (Inter-IC Sound Controller) bus is the standard
  17   interface for connecting audio devices, such as audio codecs.
  18
  19 properties:
  20   compatible:
  21     const: atmel,sama5d2-i2s
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   clocks:
  30     items:
  31       - description: Peripheral clock
  32       - description: Generated clock (Optional)
  33       - description: I2S mux clock (Optional). Set
  34           with gclk when Master Mode is required.
  35     minItems: 1
  36
  37   clock-names:
  38     items:
  39       - const: pclk
  40       - const: gclk
  41       - const: muxclk
  42     minItems: 1
  43
  44   dmas:
  45     items:
  46       - description: TX DMA Channel
  47       - description: RX DMA Channel
  48
  49   dma-names:
  50     items:
  51       - const: tx
  52       - const: rx
  53
  54 required:
  55   - compatible
  56   - reg
  57   - interrupts
  58   - dmas
  59   - dma-names
  60   - clocks
  61   - clock-names
  62
  63 additionalProperties: false
  64
  65 examples:
  66   - |
  67     #include <dt-bindings/dma/at91.h>
  68     #include <dt-bindings/interrupt-controller/arm-gic.h>
  69
  70     i2s@f8050000 {
  71         compatible = "atmel,sama5d2-i2s";
  72         reg = <0xf8050000 0x300>;
  73         interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
  74         dmas = <&dma0
  75                 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  76                 AT91_XDMAC_DT_PERID(31))>,
  77                <&dma0
  78                 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  79                 AT91_XDMAC_DT_PERID(32))>;
  80         dma-names = "tx", "rx";
  81         clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>;
  82         clock-names = "pclk", "gclk", "muxclk";
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_i2s0_default>;
  85     };