1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller.
22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and serial support
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Control and Debug functionalities.
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These nodes are described in the
50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or target-module nodes.
55 See ../../mfd/syscon.yaml for generic SysCon binding details.
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,am625-pruss # for K3 AM62x SoC family
69 - ti,am642-icssg # for K3 AM64x SoC family
70 - ti,am654-icssg # for K3 AM65x SoC family
71 - ti,j721e-icssg # for K3 J721E SoC family
72 - ti,k2g-pruss # for 66AK2G SoC family
93 This property is as per sci-pm-domain.txt.
99 The various Data RAMs within a single PRU-ICSS unit are represented as a
100 single node with the name 'memories'.
106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
108 - description: Address and size of the Data RAM0.
109 - description: Address and size of the Data RAM1.
111 Address and size of the Shared Data RAM. Note that on AM437x one
112 of two PRUSS units don't contain Shared RAM, while the second one
126 additionalProperties: false
130 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
137 - const: ti,pruss-cfg
163 coreclk-mux@[a-f0-9]+$:
165 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
166 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
167 ICSSG_ICLK. This node models this clock mux and should have the
178 - description: ICSSG_CORE Clock
179 - description: ICSSG_ICLK Clock
184 assigned-clock-parents:
187 Standard assigned-clocks-parents definition used for selecting
188 mux parent (one of the mux input).
196 additionalProperties: false
198 iepclk-mux@[a-f0-9]+$:
200 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
201 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
202 mux and should have the name "iepclk-mux".
212 - description: ICSSG_IEP Clock
213 - description: Core Clock (OCP Clock in older SoCs)
218 assigned-clock-parents:
221 Standard assigned-clocks-parents definition used for selecting
222 mux parent (one of the mux input).
230 additionalProperties: false
232 additionalProperties: false
236 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
237 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
238 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).
239 IEP is used for creating PTP clocks and generating PPS signals.
245 Real-Time Ethernet to support multiple industrial communication protocols.
246 MII-RT sub-module represented as a SysCon.
253 - const: ti,pruss-mii
259 additionalProperties: false
263 The Real-time Media Independent Interface to support multiple industrial
264 communication protocols (G stands for Gigabit). MII-G-RT sub-module
265 represented as a SysCon.
272 - const: ti,pruss-mii-g
278 additionalProperties: false
280 interrupt-controller@[a-f0-9]+$:
282 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
283 that is common to all the PRU cores. This should be represented as an
284 interrupt-controller node.
285 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
290 MDIO Node. Each PRUSS has an MDIO module that can be used to control
291 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
292 the MDIO Controller used in TI Davinci SoCs.
293 $ref: /schemas/net/ti,davinci-mdio.yaml#
296 "^(pru|rtu|txpru)@[0-9a-f]+$":
298 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
299 device through a PRU child node each. Each node can optionally be rendered
300 inactive by using the standard DT string property, "status". The ICSSG IP
301 present on K3 SoCs have additional auxiliary PRU cores with slightly
302 different IP integration.
303 $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
311 additionalProperties: false
313 # Due to inability of correctly verifying sub-nodes with an @address through
314 # the "required" list, the required sub-nodes below are commented out for now.
318 # - interrupt-controller
348 /* Example 1 AM33xx PRU-ICSS */
350 compatible = "ti,am3356-pruss";
352 #address-cells = <1>;
356 pruss_mem: memories@0 {
360 reg-names = "dram0", "dram1", "shrdram2";
363 pruss_cfg: cfg@26000 {
364 compatible = "ti,pruss-cfg", "syscon";
365 #address-cells = <1>;
367 reg = <0x26000 0x2000>;
368 ranges = <0x00 0x26000 0x2000>;
371 #address-cells = <1>;
374 pruss_iepclk_mux: iepclk-mux@30 {
377 clocks = <&l3_gclk>, /* icss_iep */
378 <&pruss_ocp_gclk>; /* icss_ocp */
383 pruss_mii_rt: mii-rt@32000 {
384 compatible = "ti,pruss-mii", "syscon";
385 reg = <0x32000 0x58>;
388 pruss_intc: interrupt-controller@20000 {
389 compatible = "ti,pruss-intc";
390 reg = <0x20000 0x2000>;
391 interrupt-controller;
392 #interrupt-cells = <3>;
393 interrupts = <20 21 22 23 24 25 26 27>;
394 interrupt-names = "host_intr0", "host_intr1",
395 "host_intr2", "host_intr3",
396 "host_intr4", "host_intr5",
397 "host_intr6", "host_intr7";
401 compatible = "ti,am3356-pru";
402 reg = <0x34000 0x2000>,
405 reg-names = "iram", "control", "debug";
406 firmware-name = "am335x-pru0-fw";
410 compatible = "ti,am3356-pru";
411 reg = <0x38000 0x2000>,
414 reg-names = "iram", "control", "debug";
415 firmware-name = "am335x-pru1-fw";
418 pruss_mdio: mdio@32400 {
419 compatible = "ti,davinci_mdio";
420 reg = <0x32400 0x90>;
421 clocks = <&dpll_core_m4_ck>;
423 bus_freq = <1000000>;
424 #address-cells = <1>;
431 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
432 #include <dt-bindings/interrupt-controller/arm-gic.h>
434 compatible = "ti,am4376-pruss1";
436 #address-cells = <1>;
440 pruss1_mem: memories@0 {
444 reg-names = "dram0", "dram1", "shrdram2";
447 pruss1_cfg: cfg@26000 {
448 compatible = "ti,pruss-cfg", "syscon";
449 #address-cells = <1>;
451 reg = <0x26000 0x2000>;
452 ranges = <0x00 0x26000 0x2000>;
455 #address-cells = <1>;
458 pruss1_iepclk_mux: iepclk-mux@30 {
461 clocks = <&sysclk_div>, /* icss_iep */
462 <&pruss_ocp_gclk>; /* icss_ocp */
467 pruss1_mii_rt: mii-rt@32000 {
468 compatible = "ti,pruss-mii", "syscon";
469 reg = <0x32000 0x58>;
472 pruss1_intc: interrupt-controller@20000 {
473 compatible = "ti,pruss-intc";
474 reg = <0x20000 0x2000>;
475 interrupt-controller;
476 #interrupt-cells = <3>;
477 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "host_intr0", "host_intr1",
485 "host_intr2", "host_intr3",
487 "host_intr6", "host_intr7";
488 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
492 compatible = "ti,am4376-pru";
493 reg = <0x34000 0x3000>,
496 reg-names = "iram", "control", "debug";
497 firmware-name = "am437x-pru1_0-fw";
501 compatible = "ti,am4376-pru";
502 reg = <0x38000 0x3000>,
505 reg-names = "iram", "control", "debug";
506 firmware-name = "am437x-pru1_1-fw";
509 pruss1_mdio: mdio@32400 {
510 compatible = "ti,davinci_mdio";
511 reg = <0x32400 0x90>;
512 clocks = <&dpll_core_m4_ck>;
514 bus_freq = <1000000>;
515 #address-cells = <1>;